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DS90CP04TLQXNOPB Datasheet(PDF) 4 Page - Texas Instruments |
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DS90CP04TLQXNOPB Datasheet(HTML) 4 Page - Texas Instruments |
4 / 25 page DS90CP04 SNLS154I – JANUARY 2002 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Pin I/O, Type Description Name Number DIGITAL CONTROL INTERFACE SCLK 6 I, LVCMOS Control clock to latch in programming data at SI. SCLK can be 0 MHz to 100 MHz. SCLK should be burst of clock pulses active only while accessing the device. After completion of programming, SCLK should be kept at logic low to minimize potential noise injection into the high-speed differential data paths. SI / SEL1 7 I, LVCMOS Programming data to select the switch configuration. Data is latched into the input buffer register at the rising edge of SCLK. SEL0 5 I, LVCMOS Programming data to select the switch configuration. CSO 18 O, LVCMOS With MODE low, control data is shifted out at CSO (RSO) for cascading to the next device RSO 2 in the serial chain. The control data at CSO (RSO) is identical to that shifted in at SI with the exception of the device column (row) address being decremented by one internally before propagating to the next device in the chain. CSO (RSO) is clocked out at the rising edge of SCLK. CSCLK 19 O, LVCMOS With MODE low, these pins function as a buffered control clock from SCLK. CSCLK RSCLK 3 (RSCLK) is used for cascading the serial control bus to the next device in the serial chain. LOAD 22 I, LVCMOS When LOAD is high and SCLK makes a LH transition, the device transfers the programming data in the load register into the configuration registers. The new switch configuration for all outputs takes effect. LOAD needs to remain high for only one SCLK cycle to complete the process, holding LOAD high longer repeats the transfer to the configuration register. MODE 23 I, LVCMOS When MODE is low, the SCLK is active and a buffered SCLK signal is present at the CLKOUT output. When MODE is high, the SCLK signal is uncoupled from register and state machine internals. Internal registers will see an active low signal until MODE is brought Low again. POWER VDD 1, 8, 17, I, Power VDD = 2.5V ±5%. At least 4 low ESR 0.01 µF bypass capacitors should be connected from 24 VDD to GND plane. GND 4, 20, 21, I, Power Ground reference to LVDS and CMOS circuitry. DAP DAP is the exposed metal contact at the bottom of the WQFN-32 package. The DAP is used as the primary GND connection to the device. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance. Serial Interface Truth Table LOAD MODE SCLK Resulting Action 0 0 LH The current state on SI is clocked into the input shift register. 0 1 LH Uncouples SCLK input from internal registers and state machine inputs. The RSCLK and CSCLK outputs will drive an active Low signal until MODE is brought Low again. See Configuration Select Truth Table below. LH 0 X Loads OUT1–OUT4 configuration information from last valid frame. Places contents of load register into the configuration register. The switch configuration is updated asynchronously from the SCLK input. 1 1 LH Uncouples SCLK input from internal registers and state machine inputs. The RSCLK and CSCLK outputs will drive an active Low signal until MODE is brought Low again. See Configuration Select Truth Table below. Configuration Select Truth Table MODE SEL1 SEL0 Resulting Action 0 X X The SEL0/1 pins only function in configuration select mode. See below. 1 0 0 Distribution: IN1 - OUT1 OUT2 OUT3 OUT4 1 0 1 Distribution: IN2 - OUT1 OUT2 OUT3 OUT4 1 1 0 Redundancy: IN1 - OUT1 OUT2 and IN3 - OUT3 OUT4 1 1 1 Broadside: IN1 - OUT1, IN2 - OUT2, IN3 - OUT3, IN4 - OUT4 4 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 |
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