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CP3BT23G18AWMXNOPB Datasheet(PDF) 2 Page - Texas Instruments |
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CP3BT23G18AWMXNOPB Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 324 page  CP3BT23 SNOSCX3A – JULY 2013 – REVISED JANUARY 2014 www.ti.com 2 Features CPU Features • Fully static RISC processor core, capable of • Dual clock and reset operating from 0 to 24 MHz with zero wait/hold • Power-down modes states • Up to 56 general-purpose I/O pins (shared with • Minimum 41.7 ns instruction cycle time with a on-chip peripheral I/O) 24 MHz internal clock frequency, based on a 12 • Programmable I/O pin characteristics: TRI- MHz external input STATE output, push-pull output, weak pull-up • 47 independently vectored peripheral interrupts input, high-impedance input On-Chip Memory • Schmitt triggers on general-purpose inputs • 256K bytes reprogrammable Flash program • Multi-Input Wake-Up (MIWU) capability memory • Flexible I/O • 8K bytes Flash data memory Power Supply • 32K bytes of static RAM data memory • I/O port operation at 2.5V to 3.3V • Addresses up to 12M bytes of external memory • Core logic operation at 2.5V Broad Range of Hardware Communications • On-chip power-on reset Peripherals Temperature Range • Bluetooth Lower Link Controller (LLC) • –40°C to +85°C (Industrial) including a shared 4.5K byte Bluetooth RAM Packages and 1K byte Bluetooth Sequencer RAM • LQFP-128, LQFP-144 • ACCESS.bus serial bus (compatible with Complete Development Environment Philips I2C bus) • Pre-integrated hardware and software support • Dual CAN interface with 15 message buffers for rapid prototyping and production conforming to CAN specification 2.0B active • Integrated environment • 8/16-bit SPI, Microwire/Plus serial interface • Project manager • Four-channel Universal Asynchronous Receiver/Transmitter (UART), one channel has • Multi-file C source editor USART capability • High-level C source debugger • Advanced Audio Interface (AAI) to connect to • Comprehensive, integrated, one-stop technical external 8/ 13-bit PCM Codecs as well as to support ISDN-Controllers through the IOM-2 interface Bluetooth Protocol Stack (slave only) • Applications can interface to the high-level • CVSD/PCM converter supporting one protocols or directly to the low-level Host bidirectional audio connection Controller Interface (HCI) General-Purpose Hardware Peripherals • Transport layer support allows HCI command- • 12-bit A/D Converter (ADC) based interface over UART port • Dual 16-bit Multi-Function Timer (MFT) • Baseband (Link Controller) hardware minimizes • Versatile Timer Unit with four subsystems the bandwidth demand on the CPU (VTU) • Link Manager (LM) • Four-channel DMA controller • Logical Link Control and Adaptation Protocol • Timing and Watchdog Unit (L2CAP) • Random Number Generator peripheral • Service Discovery Protocol (SDP) Extensive Power and Clock Management • RFCOMM Serial Port Emulation Protocol Support • All packet types, piconet, and scatternet • On-chip Phase Locked Loop functionality supported • Support for multiple clock options 2 Features Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CP3BT23 |
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