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CP3BT23Y98AWMNOPB Datasheet(PDF) 8 Page - Texas Instruments |
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CP3BT23Y98AWMNOPB Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 324 page  CP3BT23 SNOSCX3A – JULY 2013 – REVISED JANUARY 2014 www.ti.com 3.16 MULTI-FUNCTION TIMER The Multi-Function Timer (MFT) module contains a pair of 16-bit timer/counter registers. Each timer/counter unit can be configured to operate in any of the following modes: • Processor-Independent Pulse Width Modulation (PWM) mode: Generates pulses of a specified width and duty cycle and provides a general-purpose timer/ counter. • Dual Input Capture mode: Measures the elapsed time between occurrences of external event and provides a general-purpose timer/counter. • Dual Independent Timer mode: Generates system timing signals or counts occurrences of external events. • Single Input Capture and Single Timer mode: Provides one external event counter and one system timer. 3.17 TIMING AND WATCHDOG MODULE The Timing and Watchdog Module (TWM) contains a RealTime timer and a Watchdog unit. The Real- Time Clock Timing function can be used to generate periodic real-time based system interrupts. The timer output is one of 16 inputs to the Multi-Input Wake-Up module which can be used to exit from a power- saving mode. The Watchdog unit is designed to detect the application program getting stuck in an infinite loop resulting in loss of program control or “runaway” programs. When the watchdog triggers, it resets the device. The TWM is clocked by the low-speed System Clock. 3.18 VERSATILE TIMER UNIT The Versatile Timer Unit (VTU) module contains four independent timer subsystems, each operating in either dual 8bit PWM configuration, as a single 16-bit PWM timer, or a 16-bit counter with two input capture channels. Each of the four timer subsystems offer an 8-bit clock prescaler to accommodate a wide range of frequencies. 3.19 TRIPLE CLOCK AND RESET The Triple Clock and Reset module generates a high-speed main System Clock from an external crystal network. It also provides the main system reset signal and a power-on reset function. This module generates a slow System Clock (32.768 kHz) from an optional external crystal network. The Slow Clock is used for operating the device in a low-power mode. The 32.768 kHz external crystal network is optional, because the low speed System Clock can be derived from the highspeed clock by a prescaler. Also, two independent clocks divided down from the high speed clock are available on output pins. The Triple Clock and Reset module provides the clock signals required for the operation of the various CP3BT23 onchip modules. From external crystal networks, it generates the Main Clock, which can be scaled up to 24 MHz from an external 12 MHz input clock, and a 32.768 kHz secondary System Clock. The 12 MHz external clock is primarily used as the reference frequency for the on-chip PLL. The clock for modules which require a fixed clock rate (e.g. the Bluetooth LLC and the CVSD/PCM transcoder) is also generated through prescalers from the 12 MHz clock. The PLL may be used to drive the high-speed System Clock through a prescaler. Alternatively, the high speed System Clock can be derived directly from the 12 MHz Main Clock. In addition, this module generates the device reset by using reset input signals coming from an external reset and various on-chip modules. 8 Device Overview Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CP3BT23 |
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