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COP8SGH5 Datasheet(PDF) 10 Page - Texas Instruments |
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COP8SGH5 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 82 page  COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) (2) Supply Voltage (VCC) 7V Voltage at Any Pin −0.3V to VCC +0.3V Total Current into VCC Pin (Source) 100 mA Total Current out of GND Pin (Sink) 110 mA Storage Temperature Range −65°C to +140°C ESD Protection Level 2kV (Human Body Model) (1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. DC Electrical Characteristics −40°C ≤ TA ≤ +125°C unless otherwise specified. Parameter Conditions Min Typ Max Units Operating Voltage 4.5 5.5 V Power Supply Rise Time 10 50 x 106 ns VCC Start Voltage to Ensure POR 0 0.25 V Power Supply Ripple(1) Peak-to-Peak 0.1 Vcc V Supply Current(2) CKI = 10 MHz VCC = 5.5V, tC = 1 μs 6.0 mA CKI = 4 MHz VCC = 4.5V, tC = 2.5 μs 2.1 mA HALT Current(3) VCC = 5.5V, CKI = 0 MHz <4 10 μA IDLE Current(2) CKI = 10 MHz VCC = 5.5V, tC = 1 μs 1.5 mA CKI = 4 MHz VCC = 4.5V, tC = 2.5 μs 0.8 mA Input Levels (VIH, VIL) RESET Logic High 0.8 Vcc V Logic Low 0.2 Vcc V CKI, All Other Inputs 0.7 Vcc Logic High V Logic Low 0.2 Vcc V Internal Bias Resistor for the 0.5 1 2 M Ω Crystal/Resonator Oscillator CKI Resistance to VCC or GND when R/C VCC = 5.5V 5 8 11 k Ω Oscillator is selected Hi-Z Input Leakage VCC = 5.5V −5 +5 μA Input Pullup Current VCC = 5.5V, VIN = 0V −35 −400 μA G and L Port Input Hysteresis VCC = 5.5V 0.25 Vcc V (1) Maximum rate of voltage change must be < 0.5 V/ms. (2) Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, External Oscillator, inputs connected to VCC and outputs driven low but not connected to a load. (3) The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal or external configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. 10 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: COP8SGE5 COP8SGE7 COP8SGH5 COP8SGK5 COP8SGR5 COP8SGR7 |
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