AFE5801

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SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010

DIGITAL CHARACTERISTICS

(1)

The dc specifications refer to the condition where the digital outputs are not switching, but permanently at a valid logic level 0

100

Ω.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS (PDN, RESET, SCLK, SDATA, SEN, SYNC)

High-level input voltage

1.4

3.6

V

Low-level input voltage

0.8

V

High-level input current

10

mA

Low-level input current

10

mA

Input capacitance

4

pF

High-level output voltage

1375

mV

Low-level output voltage

1025

mV

270

380

490

mV

0.9

1.15

1.5

V

Output capacitance inside the device, from either output to

Output capacitance

2

pF

DVSS.

DIGITAL OUTPUTS (SDOUT)

High-level output voltage

1.6

1.8

V

Low-level output voltage

0

0.2

V

Output impedance

50 ±25%

Ω

(1)

All LVDS specifications have been characterized but not tested at production. For clock input levels, see the Recommended Operating

Conditions table.

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