Electronic Components Datasheet Search |
|
ADS1252U2K5 Datasheet(PDF) 2 Page - Texas Instruments |
|
ADS1252U2K5 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 22 page ADS1252 2 SBAS127D www.ti.com SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY ADS1252 SO-8 D –40 °C to +85°C ADS1252U ADS1252U Rails, 100 "" " " " ADS1252U/2K5 Tape and Reel, 2500 Analog Input: Current ............................................... ±100mA, Momentary ±10mA, Continuous Voltage .................................... GND – 0.3V to VDD + 0.3V VDD to GND ............................................................................ –0.3V to 6V VREF Voltage to GND ............................................... –0.3V to VDD + 0.3V Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V Lead Temperature (soldering, 10s) .............................................. +300 °C Power Dissipation (any package) ................................................. 500mW NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Top View SO PIN DESCRIPTIONS PIN NAME PIN DESCRIPTION 1+VIN Analog Input: Positive Input of the Differen- tial Analog Input 2 –VIN Analog Input: Negative Input of the Differ- ential Analog Input 3+VDD Input: Power-Supply Voltage, +5V 4 CLK Digital Input: Device System Clock. The system clock is in the form of a CMOS- compatible clock. This is a Schmitt-Trigger input. 5 DOUT/DRDY Digital Output: Serial Data Output/Data Ready. A logic LOW on this output indi- cates that a new output word is available from the ADS1252 data output register. The serial data is clocked out of the serial data output shift register using SCLK. 6 SCLK Digital Input: Serial Clock. The serial clock is in the form of a CMOS-compatible clock. The serial clock operates independently from the system clock, therefore, it is pos- sible to run SCLK at a higher frequency than CLK. The normal state of SCLK is LOW. Holding SCLK HIGH will either ini- tiate a modulator reset for synchronizing multiple converters or enter power-down mode. This is a Schmitt-Trigger input. 7 GND Input: Ground 8VREF Analog Input: Reference Voltage Input +V IN ADS1252U GND –V IN V REF +V DD SCLK DOUT/DRDY CLK 1 2 3 4 8 7 6 5 ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. |
Similar Part No. - ADS1252U2K5 |
|
Similar Description - ADS1252U2K5 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |