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ADS1251U2K5 Datasheet(PDF) 9 Page - Texas Instruments |
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ADS1251U2K5 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 24 page  ADS1251 9 SBAS184D www.ti.com frequency must be 19.200kHz, and this sets the data output rate to 50Hz (see Table I and Figure 4). For 60Hz rejection, the system CLK frequency must be 23.040kHz, and this sets the data output rate to 60Hz (see Table I and Figure 5). If both 50Hz and 60Hz rejection is required, then the system CLK must be 3.840kHz; this sets the data output rate to 10Hz and rejects both 50Hz and 60Hz (see Table I and Figure 6). There is an additional benefit in using a lower data output rate. It provides better rejection of signals in the frequency band of interest. For example, with a 50Hz data output rate, a significant signal at 75Hz may alias back into the passband at 25Hz. This is due to the fact that rejection at 75Hz may only be 66dB in the stopband—frequencies higher than the first notch frequency (see Figure 4). However, setting the data output rate to 10Hz provides 135dB rejection at 75Hz (see Figure 6). A similar benefit is gained at frequencies near the data output rate (see Figures 7, 8, 9, and 10). For example, with a 50Hz data output rate, rejection at 55Hz may only be 105dB (see Figure 7). With a 10Hz data output rate, however, rejection at 55Hz will be 122dB (see Figure 8). If a slower data output rate does not meet the system require- ments, then the analog front-end can be designed to provide the needed attenuation to prevent aliasing. Additionally, the data output rate may be increased and additional digital filtering may be done in the processor or controller. Application note SBAA103, A Spreadsheet to Calculate the Frequency Response of the ADS1250-54, available for down- load from TI’s web site at www.ti.com, provides a simple tool for calculating the ADS1250 frequency response for any CLK frequency. The digital filter is described by the following transfer function: Hf f f f f or Hz z z MOD MOD () sin •• • sin • () – •– – – = = ( ) π π 64 64 1 64 1 5 64 1 5 The digital filter requires five conversions to fully settle. The modulator has an oversampling ratio of 64; therefore, it requires 5 • 64, or 320 modulator results (or clocks) to fully settle. As the modulator clock is derived from the system CLK (modulator clock = CLK ÷ 6), the number of system clocks required for the digital filter to fully settle is 5 • 64 • 6, or 1920 CLKs. This means that any significant step change at the analog input requires five full conversions to settle. However, if the step change at the analog input occurs asynchronously to the DOUT/DRDY pulse, six conversions are required to ensure full settling. CONTROL LOGIC The control logic is used for communications and control of the ADS1251. Power-Up Sequence Prior to power-up, all digital and analog input pins must be LOW. At the time of power-up, these signal inputs can be biased to a voltage other than 0V; however, they should never exceed +VDD. Once the ADS1251 powers up, the DOUT/DRDY line will pulse LOW on the first conversion for which the data is valid from the analog input signal. DOUT/DRDY The DOUT/DRDY output signal alternates between two modes of operation. The first mode of operation is the Data Ready mode (DRDY) to indicate that new data have been loaded into the data output register and are ready to be read. The second mode of operation is the Data Output (DOUT) mode and is used to serially shift data out of the Data Output Register (DOR). See Figure 11 for the time domain partition- ing of the DRDY and DOUT function. See Figure 12 for the basic timing of DOUT/DRDY. During the time defined by t2, t3, and t4, the DOUT/DRDY pin functions in DRDY mode. The state of the DOUT/DRDY pin |
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