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ADC12H038 Datasheet(PDF) 9 Page - Texas Instruments

Part # ADC12H038
Description  Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12H038 Datasheet(HTML) 9 Page - Texas Instruments

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ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
www.ti.com
SNAS080K – JULY 1999 – REVISED MARCH 2013
DC and Logic Electrical Characteristics (continued)
The following specifications apply for V
+ = V
A+ = VD+ = +5.0 VDC, VREF+ = +4.096 VDC, VREF− = 0 VDC, 12-bit + sign
conversion mode, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK = fSK = 5 MHz for
the ADC12030, ADC12032, ADC12034 and ADC12038, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-
differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface
limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
(1)(2)(3)
Units
Parameter
Test Conditions
Typical (4)
Limits (5)
(Limits)
VOUT(0)
Logical “0” Output Voltage
V+ = 4.5V, IOUT = 1.6 mA
0.4
V (max)
VOUT = 0V
−0.1
−3.0
µA (max)
IOUT
TRI-STATE Output Current
VOUT = 5V
0.1
3.0
µA (max)
+ISC
Output Short Circuit Source Current
VOUT = 0V
14
6.5
mA (min)
−ISC
Output Short Circuit Sink Current
VOUT = VD+
16
8.0
mA (min)
POWER SUPPLY CHARACTERISTICS
Digital Supply Current
Awake
1.6
2.5
mA (max)
ADC12030, ADC12032, ADC12034 and
CS = HIGH, Powered Down, CCLK on
600
µA
ADC12038
CS = HIGH, Powered Down, CCLK off
20
µA
ID+
Digital Supply Current
Awake
2.3
3.2
mA
ADC12H030, ADC12H032, ADC12H034
CS = HIGH, Powered Down, CCLK on
0.9
mA
and ADC12H038
CS = HIGH, Powered Down, CCLK off
20
µA
Awake
2.7
4.0
mA (max)
IA+
Positive Analog Supply Current
CS = HIGH, Powered Down, CCLK on
10
µA
CS = HIGH, Powered Down, CCLK off
0.1
µA
Awake
70
µA
IREF
Reference Input Current
CS = HIGH, Powered Down
0.1
µA
AC Electrical Characteristics
The following specifications apply for V
+ = V
A+ = VD+ = +5.0 VDC, VREF+ = +4.096 VDC, VREF− = 0 VDC, 12-bit + sign
conversion mode, tr = tf = 3 ns, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK = fSK
= 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, RS = 25Ω, source impedance for VREF+ and VREF− ≤
25
Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
(1)
Typical
ADC12H030/2/4/8
ADC12030/2/4/8
Units
Parameter
Test Conditions
(2)
Limits (3)
Limits (3)
(Limits)
fCK
Conversion Clock (CCLK)
10
8
5
MHz (max)
Frequency
1
MHz (min)
Serial Data Clock SCLK Frequency
10
8
5
MHz (max)
fSK
0
Hz (min)
40
40
% (min)
Conversion Clock Duty Cycle
60
60
% (max)
40
40
% (min)
Serial Data Clock Duty Cycle
60
60
% (max)
12-Bit + Sign or 12-
44(tCK)
44(tCK)
(max)
44(tCK)
Bit
5.5
8.8
µs (max)
tC
Conversion Time
21(tCK)
21(tCK)
(max)
8-Bit + Sign or 8-Bit
21(tCK)
2.625
4.2
µs (max)
(1)
Timing specifications are tested at the TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE output
voltage is forced to 1.4V.
(2)
Typical figures are at TJ = TA = 25°C and represent most likely parametric norm.
(3)
Tested limits are specified to AOQL (Average Outgoing Quality Level).
Copyright © 1999–2013, Texas Instruments Incorporated
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Product Folder Links: ADC12030 ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032 ADC12H034
ADC12H038


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