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ADS6425IRGC25 Datasheet(PDF) 11 Page - Texas Instruments |
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ADS6425IRGC25 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 60 page  DESCRIPTION OF PARALLEL PINS ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 Table 3. SCLK, SDATA Control Pins SCLK SDATA DESCRIPTION LOW LOW NORMAL conversion. SYNC - ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the LOW HIGH deserialized data to the frame boundary. See Capture Test Patterns for details. POWER DOWN –Global power down, all channels of the ADC are powered down, including internal references, HIGH LOW PLL and output buffers. DESKEW - ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure HIGH HIGH deserializer uses the right clock edge. See Capture Test Patterns for details. Table 4. SEN Control Pin SEN DESCRIPTION 0 External reference and 0 dB coarse gain (full-scale = 2V pp) (3/8)LVDD External reference and 3.5 dB coarse gain (full-scale = 1.34V pp) (5/8)LVDD Internal reference and 3.5 dB coarse gain (full-scale = 1.34V pp) LVDD Internal reference and 0 dB coarse gain (full-scale = 2V pp) Independent of the programming mode used, after power-up the parallel pins PDN, CFG1 to CFG4 will automatically configure the device as per the voltage applied (Table 5 to Table 9). Table 5. PDN Control Pin PDN DESCRIPTION 0 Normal operation AVDD Power down global Table 6. CFG1 Control Pin CFG1 DESCRIPTION 0 (default) DDR Bit clock and 1-wire interface +200mV (3/6)LVDD Not used ±200mV (5/6)LVDD SDR Bit clock and 2-wire interface ±200mV LVDD DDR Bit clock and 2-wire interface - 200mV Table 7. CFG2 Control Pin CFG2 DESCRIPTION 0 (default) 12x Serialization and capture at falling edge of bit clock (only with SDR bit clock) +200mV (3/6)LVDD 14x Serialization and capture at falling edge of bit clock (only with SDR bit clock) ±200mV (5/6)LVDD 14x Serialization and capture at rising edge of bit clock (only with SDR bit clock) ±200mV LVDD 12x Serialization and capture at rising edge of bit clock (only with SDR bit clock) - 200mV Table 8. CFG3 Control Pin CFG3 RESERVED - TIE TO GROUND Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): ADS6425 |
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