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ADS8201IRGET Datasheet(PDF) 4 Page - Texas Instruments |
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ADS8201IRGET Datasheet(HTML) 4 Page - Texas Instruments |
4 / 36 page IN4 IN5 IN6 IN7 RST BUSY/INT ADCIN AGND REFGND REF VA VD 1 2 3 4 5 6 18 17 16 15 14 13 ADS8201 ThermalPad (BottomSide) (1) ADS8201 SLAS534B – JULY 2009 – REVISED MAY 2010 www.ti.com PIN CONFIGURATION RGE PACKAGE QFN-24 (TOP VIEW) (1) Thermal pad should be tied to AGND. PIN DESCRIPTIONS PIN NAME NO. I/O DESCRIPTION IN4 1 I Input channel single-ended 4 or differential pair 3 IN5 2 I Input channel single-ended 5 or differential pair 3 IN6 3 I Input channel single-ended 6 or differential pair 4 IN7 4 I Input channel single-ended 7 or differential pair 4 RST 5 I External hardware reset Status output. If programmed as the BUSY pin, this pin is low (default) when a conversion is in progress. If BUSY/INT 6 O programmed as an interrupt (INT), this pin is low for a preprogrammed duration after the end of a conversion and valid data are to be output. The polarity of either BUSY or INT is programmable. SCLK 7 I Serial interface clock CS 8 I Chip select input for SPI interface slave select (SS) SDI 9 I Serial data in SDO 10 O Serial data out DGND 11 I/O Interface ground CONVST 12 I Starts conversion VD 13 I Interface supply VA 14 I Analog supply (+2.2VDC to +5.5VDC) REF 15 I External reference input REFGND 16 I/O Reference ground AGND 17 I/O Analog ground ADCIN 18 I ADC input PGAOUT 19 O Mux output. Output can be further filtered before sending to ADCIN. PGAREF 20 I PGA Reference IN0 21 I Analog channel single-ended 0 or differential pair 0 IN1 22 I Analog channel single-ended 1 or differential pair 0 IN2 23 I Analog channel single-ended 2 or differential pair 1 IN3 24 I Analog channel single-ended 3 or differential pair 1 4 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8201 |
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