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ADS7882IPFBR Datasheet(PDF) 5 Page - Texas Instruments |
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ADS7882IPFBR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 30 page TIMING REQUIREMENTS ADS7882 www.ti.com ........................................................................................................................................................................................... SLAS630 – DECEMBER 2008 All specifications typical at –40°C to 85°C, +VA = +5 V, +VBD = +5 V (1) (2) (3) (4) PARAMETER MIN TYP MAX UNIT REF FIG. t(conv) Conversion time 280 ns 5 t(acq) Acquisition time 53 ns 5 SAMPLING AND CONVERSION START th1 Hold time CS low to CONVST high (with BUSY high) 10 ns 3 td1 Delay CONVST high to acquisition start 2 4 5 ns 1 th2 Hold time, CONVST high to CS high with BUSY low 10 ns 1 th3 Hold time, CONVST low to CS high 10 ns 1 td2 Delay CONVST low to BUSY high 40 ns 1 tw3 CS width for acquisition or conversion to start 20 ns 2 td3 Delay CS low to acquisition start with CONVST high 2 4 5 ns 2 tw1 Pulse width, from CS low to CONVST low for acquisition to start 20 ns 2 td4 Delay CS low to BUSY high with CONVST low 40 ns 2 Quiet sampling time(3) 25 ns CONVERSION ABORT ts1 Setup time CONVST high to CS low with BUSY high 15 ns 4 td5 Delay time CS low to BUSY low with CONVST high 20 ns 4 DATA READ td6 Delay RD low to data valid with CS low 25 ns td7 Delay BYTE high to LSB word valid with CS and RD low 25 ns 5 td9 Delay time RD high to data 3-state with CS low 25 ns 5 td11 Delay time end of conversion to BUSY low 20 ns 5 t1 Quiet sampling time RD high to CONVST low 20 ns 5 td8 Delay CS low to data valid with RD low 25 ns 5 td10 Delay CS high to data 3-state with RD low 25 ns 6 t2 Quiet sampling time CS low to CONVST low 25 ns 6 BACK-TO-BACK CONVERSION td12 Delay BUSY low to data valid 10 ns 7, 8 tw4 Pulse width, CONVST high 63 ns 7, 8 tw5 Pulse width, CONVST low 20 ns 7 POWER DOWN/RESET tw6 Pulse width, low for PWD/RST to reset the device 45 6140 ns 10 tw7 Pulse width, low for PWD/RST to power down the device 7200 ns 9 td13 Delay time, power up after PWD/RST is high 25 ns 9 (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagram. (3) Quiet period before conversion start, no data bus activity including data bus 3-state is allowed in this period. (4) All timings are measured with 20 pF equivalent loads on all data bits and BUSY pin. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): ADS7882 |
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