ADS803

3

SBAS074B

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ADS803E

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUTS

Logic Family

CMOS Compatible

Convert Command

Start Conversion

Rising Edge of Convert Clock

100

µA

±10

µA

High Level Input Voltage

+3.5

V

Low Level Input Voltage

+1.0

V

Input Capacitance

5pF

DIGITAL OUTPUTS

Logic Family

CMOS/TTL Compatible

V

Logic Coding

Straight Offset Binary

Low Output Voltage

0.1

V

Low Output Voltage

0.4

V

High Output Voltage

+4.5

V

High Output Voltage

+2.4

V

3-State Enable Time

OE = L

20

40

ns

3-State Disable Time

OE = H

2

10

ns

Output Capacitance

5pF

ACCURACY (5Vp-p Input Range)

Zero Error (Referred to –FS)

At 25

°C

0.2

±1.5

%FS

Zero Error Drift (Referred to –FS)

±5

ppm/

°C

At 25

°C

±2.0

%FS

±15

ppm/

°C

At 25

°C

±1.5

%FS

±15

ppm/

°C

Power-Supply Rejection of Gain

∆V

60

82

dB

Reference Input Resistance

1.6

k

Ω

At 25

°C

±35

mV

At 25

°C

±14

mV

POWER-SUPPLY REQUIREMENTS

Operating

+4.7

+5.0

5.3

V

Operating

23

27

mA

Power Dissipation

Operating

115

135

mW

Thermal Resistance,

θ

JA

SSOP-28

50

°C/W

NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full-scale. (3) 2-tone intermodulation

distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope. (4) Effective

number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (5) Internal 50k

Ω pull-down resistor. (6) Includes internal reference. (7) Excludes internal reference.