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ADS1203IRGTTG4 Datasheet(PDF) 8 Page - Texas Instruments |
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ADS1203IRGTTG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 34 page ADS1203 SBAS318C − JUNE 2004 − REVISED JANUARY 2008 www.ti.com 8 Internal MCLK Internal MDATA MDATA t C1 t W1 1 0 110 0 Figure 3. Mode 2 Operation TIMING CHARACTERISTICS: MODE 2 Over recommended operating free-air temperature range at −40 °C to +125°C, AVDD = BVDD = +5V(1) or AVDD = +5V, BVDD = +3V(2) or VDD = +5V(1), unless otherwise noted. PARAMETER MODE MIN MAX UNIT tC1 Clock period 2 91 111 ns tW1 Clock high time 2 (tC1/2) − 5 (tC1/2) + 5 ns (1) Applicable for 5.0V nominal supply: BV DD (min) = 4.5V and BVDD (max) = 5.5V. (2) Only for QFN package. Applicable for 3.0V nominal supply: BV DD (min) = 2.7V and BVDD (max) = 3.6V. CLKOUT(1) NOTE: (1) CLKOUT availble only on QFN package. MDAT t C1 t W2 t D3 t C2 t W1 t D1 t D2 t D4 MCLK Figure 4. Mode 3 Operation TIMING CHARACTERISTICS: MODE 3 Over recommended operating free-air temperature range at −40 °C to +125°C, AVDD = BVDD = +5V(1) or AVDD = +5V, BVDD = +3V(2) or VDD = +5V(1), unless otherwise noted. PARAMETER MIN MAX UNIT tC1 MCLK period 41.6 1000 ns tW1 MCLK high time 10 tC1 − 10 ns tC2 CLKOUT period 2 × tC1 2 × tC1 ns tW2 CLKOUT high time (tC2/2) − 5 (tC2/2) + 5 ns tD1 CLKOUT rising edge delay after MCLK rising edge 0 10 ns tD2 CLKOUT falling edge delay after MCLK rising edge 0 10 ns tD3 Data valid delay after rising edge of CLKOUT −2 +2 ns tD4 Data valid delay after rising edge of MCLK 0 10 ns NOTE: Input signal is specified with tR = tF = 5ns (10% to 90% of BVDD or VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagram. (1) Applicable for 5.0V nominal supply: BV DD (min) = 4.5V and BVDD (max) = 5.5V. (2) Only for QFN package. Applicable for 3.0V nominal supply: BV DD (min) = 2.7V and BVDD (max) = 3.6V. |
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