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DRDY

SYNC

DOUT[15:0]

t

9

t

10

t

11

CLK

ValidData

ADS1610

SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006

Figure 3. Reset Timing

DESCRIPTION

MIN

TYP MAX

UNIT

16.667

ns

1

60

MHz

CLK pulse width, high or low

45%

55%

ns

CLK to DRDY high (propagation delay)

12

ns

DRDY pulse width, high or low

ns

Previous data valid (hold time)

0

ns

New data valid (setup time)

5

ns

RD and/or CS inactive (high) to DOUT high impedance

15

ns

RD and/or CS active (low) to DOUT active

15

ns

Delay from SYNC active (low) to all-zero DOUT[15:0]

12

ns

Delay from SYNC inactive (high) to non-zero DOUT[15:0]

21

DRDY

Delay from SYNC inactive (high )to valid DOUT[15:0] (time – 55 DRDY cycles; required for digital

55

DRDY

filter to settle).

(1)

Output load = 10pF|| 500k

Ω.

7

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