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ADS5232IPAGG4 Datasheet(PDF) 9 Page - Texas Instruments

Part # ADS5232IPAGG4
Description  Dual, 12-Bit, 65MSPS, 3.3V Analog-to-Digital Converter
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS5232IPAGG4 Datasheet(HTML) 9 Page - Texas Instruments

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SERIAL INTERFACE TIMING
NOTE: Data is shifted in MSB first.
Start Sequence
t
1
t
7
t
6
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
t
2
t
3
t
4
t
5
CLK
SEN
SCLK
SDATA
Outputs change on
next rising clock edge
after SEN goes high.
Data latched on
each rising edge of SCLK.
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
TIMING CHARACTERISTICS (continued)
Typical values at T
A = +25°C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% duty
cycle, and total capacitive loading = 10pF, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNITS
t2 Data Hold Time
200
250
ns
tD Data Latency
6
Clocks
tDR, tDF Data Rise/Fall Time
0.5
2
3.5
ns
Data Valid (DV) Duty Cycle
30
45
55
%
tDV Input Clock Rising to DV Fall Edge
200
225
250
ns
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
t1
Serial CLK Period
50
ns
t2
Serial CLK High Time
20
ns
t3
Serial CLK Low Time
20
ns
t4
Data Setup Time
5
ns
t5
Data Hold Time
5
ns
t6
SEN Fall to SCLK Rise
8
ns
t7
SCLK Rise to SEN Rise
8
ns
9
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