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ADS7850IRTET Datasheet(PDF) 9 Page - Texas Instruments |
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ADS7850IRTET Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 43 page  1 2 13 14 15 16 22 23 24 25 26 27 28 30 SCLK CS D9 D8 D7 D6 D5 D4 SDO-A SDO-B ADS8350 tSU_CSCK tDV_CSDO tHT_CKDO tSU_DOCK tDZ_CSDO Sample N Sample N + 1 tACQ tCONV tTHROUGHPUT Data From Sample N tPH_CS 30 31 D15 D14 17 D3 D2 D1 D0 tPH_CK tPL_CK tSCLK tD_CKCS 32 D7 D6 D5 D4 SDO-A SDO-B ADS7850 Data From Sample N D13 D12 D3 D2 D1 D0 D5 D4 SDO-A SDO-B ADS7250 Data From Sample N D11 D10 D3 D2 D1 D0 0 0 0 0 0 0 ADS8350, ADS7850, ADS7250 www.ti.com SBAS580C – MAY 2013 – REVISED JUNE 2014 6.9 Timing Characteristics Minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3 V, and tDATA = 750 kSPS, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fCLK = max 750 kSPS fTHROUGHPUT Sample taken to data read fCLK = max 1.33 µs fCLK CLOCK frequency fTHROUGHPUT = max 24 MHz tCLK CLOCK period fTHROUGHPUT = max 41.66 ns tPH_CK CLOCK high time 0.4 0.6 tCLK tPL_CK CLOCK low time 0.4 0.6 tCLK tCONV Conversion time 590 ns ADS8350, fCLK = max 120 ns tACQ Acquisition time ADS7850, fCLK = max 100 ns ADS7250, fCLK = max 70 ns tPH_CS CS high time 20 ns ADS8350 120 ns tPH_CS_SHRT CS high time after frame abort ADS7850 100 ns ADS7250 70 ns tDV_CSDO Delay time from CS falling to data enable 12 ns tD_CKCS Delay time from last SCLK falling to CS rising 15 ns Delay time from CS rising to DOUT going to 3- tDZ_CSDO 10 ns state tSU_CSCK Setup time from CS falling to SCLK falling 15 ns tSU_DOCK Setup time from DOUT data valid to SCLK falling 5 ns Hold time: SCLK falling to (previous) data valid on tHT_CKDO 3 ns DOUT Figure 1. Timing Diagram Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: ADS8350 ADS7850 ADS7250 |
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