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SP813LCN-L Datasheet(PDF) 4 Page - Exar Corporation |
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SP813LCN-L Datasheet(HTML) 4 Page - Exar Corporation |
4 / 17 page S SP P7 70 05 5--S SP P7 70 08 8--S SP P8 81 13 3L L L Lo ow w P Po ow we err M Miiccrro op prro occe es ss so orr S Su up pe errv viis so orry y C Ciirrccu uiitts s © 2010 Exar Corporation 4/17 Rev. 2.0.0 PIN ASSIGNMENT Fig. 3: Pin Assignment PIN DESCRIPTION Name Pin Number Description SP705-SP706 SP707-SP708 SP813L SOIC MSOP SOIC MSOP DIP SOIC MR 1 3 1 3 1 Manual Reset This input triggers a reset pulse when pulled below 0.8V. This active LOW input has an internal 250µA pull-up current. It can be driven from a TTL or CMOS logic line or shorted to ground with a switch. VCC 2 4 2 4 2 +5V power supply GND 3 5 3 5 3 Ground reference for all signals PFI 4 6 4 6 4 Power-Fail Input When this voltage monitor input is less than 1.25V, PFO goes LOW. Connect PFI to ground or VCC when not in use. PFO 5 - 5 7 5 Power-Fail Output This output is LOW until PFI is less then 1.25V WDI 6 8 - - 6 Watchdog Input If this input remains HIGH or LOW for 1.6s, the internal watchdog timer times out and WDO goes LOW. Floating WDI or connecting WDI to a high-impedance tri-state buffer disables the watchdog feature. The internal watchdog timer clears whenever RESET is asserted, WDI is tri-stated, or whenever WDI sees a rising or falling edge. N.C. - - 6 8 - No Connect RESET 7 1 7 1 - Active-LOW RESET Output This output pulses LOW for 200ms when triggered and stays LOW whenever VCC is below the reset threshold (4.65V for the SP705/707/813L and 4.40V for the SP706/708). It remains LOW for 200ms after Vcc rises above the reset threshold or MR goes from LOW to HIGH. A watchdog timeout will not trigger RESET unless WDO is connected to MR. |
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