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ADC12040CIVY Datasheet(PDF) 8 Page - Texas Instruments

Part # ADC12040CIVY
Description  12-Bit, 40 MSPS, 340mW A/D Converter with Internal Sample-and-Hold
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12040CIVY Datasheet(HTML) 8 Page - Texas Instruments

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ADC12040
SNAS135G – FEBRUARY 2001 – REVISED MARCH 2013
www.ti.com
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =
+3.0V, PD = 0V, VREF = +2.0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX:
all other limits TA = TJ = 25°C
(1) (2) (3) (4)
Typical
Limits
Units
Symbol
Parameter
Conditions
(5)
(5)
(Limits)
fCLK1
Maximum Clock Frequency
50
40
MHz (min)
fCLK2
Minimum Clock Frequency
100
kHz
tCH
Clock High Time
11.25
ns (min)
tCL
Clock Low Time
11.25
ns (min)
tCONV
Conversion Latency
6
Clock Cycles
VDR = 2.5V, −45°C < TA < +85°C
16.3
ns (max)
VDR = 2.5V, TA = +25°C
12
15.9
ns (max)
tOD
Data Output Delay after Rising CLK Edge
VDR = 3.0V, −45°C < TA < +85°C
15.7
ns (max)
VDR = 3.0V, TA = +25°C
11
14.9
ns (max)
tAD
Aperture Delay
1.2
ns
tAJ
Aperture Jitter
1.2
ps rms
tDIS
Data outputs into TRI-STATE Mode
4
ns
tEN
Data Outputs Active after TRI-STATE
4
ns
tPD
Power Down Mode Exit Cycle
20
tCLK
(1)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per (). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100
mV. As an example, if VA is 4.75V, the full-scale input voltage must be ≤4.85V to ensure accurate conversions. See Figure 1
(2)
To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(3)
With the test condition for VREF = +2.0V (4VP-P differential input), the 12-bit LSB is 977 µV.
(4)
Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge.
(5)
Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average
Outgoing Quality Level).
Figure 1.
Specification Definitions
APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for
conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
Aperture jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the
total time of one period. The specification here refers to the ADC clock input signal.
COMMON MODE VOLTAGE (VCM) is the d.c. potential present at both signal inputs to the ADC.
8
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Product Folder Links: ADC12040


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