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ADC1175CIMTCX Datasheet(PDF) 6 Page - Texas Instruments |
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ADC1175CIMTCX Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 29 page  ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com CONVERTER ELECTRICAL CHARACTERISTICS The following specifications apply for AVDD = DVDD = +5.0VDC, OE = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 20MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C (1) (2) Symbol Parameter Conditions Typical(3) Limits(3) Units DC Accuracy INL Integral Non Linearity f CLK = 20 MHz ±0.5 ±1.3 LSB ( max) INL Integral Non Linearity f CLK = 30 MHz ±1.0 LSB ( max) DNL Differential Non Linearity f CLK = 20 MHz ±0.35 ±0.75 LSB ( max) DNL Differential Non Linearity f CLK = 30 MHz ±1.0 LSB ( max) Missing Codes 0 (max) EOT Top Offset −24 mV EOB Bottom Offset +37 mV Video Accuracy fin = 4.43 MHz sine wave DP Differential Phase Error 0.5 Degree fCLK = 17.7 MHz fin = 4.43 MHz sine wave DG Differential Gain Error 0.4 % fCLK = 17.7 MHz Analog Input and Reference Characteristics VRB V (min) VIN Input Range 2.0 VRT V (max) (CLK LOW) 4 CIN VIN Input Capacitance VIN = 1.5V + 0.7Vrms pF (CLK HIGH) 11 RIN RIN Input Resistance >1 M Ω BW Analog Input Bandwidth 120 MHz RRT Top Reference Resistor 360 Ω 200 Ω (min) RREF Reference Ladder Resistance VRT to VRB 300 400 Ω (max) RRB Bottom Reference Resistor 90 Ω 4.8 mA (min) VRT =VRTS, VRB =VRBS 7 9.3 mA (max) IREF Reference Ladder Current 5.4 mA (min) VRT =VRTS,VRB =AVSS 8 10.5 mA (max) VRT connected to VRTS VRT Reference Top Self Bias Voltage 2.6 V VRB connected to VRBS VRT connected to VRTS V (min) Reference Bottom Self Bias 0.55 VRB 0.6 Voltage 0.65 VRB connected to VRBS V (max) VRT connected to VRTS 1.89 V (min) 2 VRB connected to VRBS 2.15 V (max) VRTS - Self Bias Voltage Delta VRBS VRT connected to VRTS 2.3 V VRB connected to AVSS 1.0 V (min) VRT - VRB Reference Voltage Delta 2 2.8 V (max) (1) The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or to 500 mV below GND will not damage this device. However, errors in the A/D conversion can occur if the input goes above VDD or below GND by more than 50 mV. As an example, if AVDD is 4.75VDC, the full-scale input voltage must be ≤4.80VDC to ensure accurate conversions. See Figure 2. (2) To ensure accuracy, it is required that AVDD and DVDD be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. (3) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level). 6 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175 |
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