PIN

NAME

FUNCTION

10

GND

Ground

11

VON

Negative Sample/Hold Voltage Output. Do not connect for single-ended mode.

12

VOP

Sample/Hold Voltage Output. Positive output in differential mode. Also used for single-ended output.

13

GAIN

Hold Amplifier Gain Indicator. Both as output and logic input. Indicates which current mirror’s output is

active. 3.5kΩ input/output impedance.

Pin as input (mirror selection for sample/hold):

Low: Sample/hold Conversion from Current Mirror 1 (VIP1);

High: Sample/hold Conversion from Current Mirror 2 (VIP2).

Pin as output (mirror indication for sample/hold):

Low: Sample/hold Conversion from Current Mirror 1 (VIP1);

High: Sample/hold Conversion from Current Mirror 2 (VIP2).

14

ISRC/

SHDN

Dual-Purpose Pin.

ISRC: A resistor connected to this pin controls the amount of current flowing through a current source

connected to MIROUT. (

Note: During this mode of operation, the microcontroller pin (if connected)

should be in the high impedance.)

SHDN: If pulled high, sets MIROUT to high-impedance.

15

ILIMS

Current-Limit Status. Active-low signal indicating that the current-limit threshold is exceeded.

16

APDV

APD Voltage Monitor. Provides output voltage used to calculate the voltage on the APD.

17

RLIM

Resistor Limit. Connect a resistor between RLIM and GND to set the current clamp limit.

18

DIS-

CHARGE

Discharge Enable.

When sampling is deactivated and the DISCHARGE pin logic input is low, the discharge function is

disabled.

When sampling is deactivated and the DISCHARGE pin logic input is high, the discharge function is

enabled, and the DS3923 pulls current mirror outputs VIP1 and VIP2 low to ensure accurate sam-

pling.

During the sample time, the pin discaharge is internally disabled by the DS3923. See Figure 4 and

Figure 5 for more detail.

Note: The discharge function should not be used if SENXOR is a logic-high.

19

MIROUT

Current Mirror Output. Connect to APD.

20

HVG

High-Voltage NMOS FET Gate. Connect to ground if unused.

21

MIRCAP

Mirror Filter. Connect external capacitor to filter voltage at MIROUT.

22

MIRIN

Current Mirror Input. Connect to high voltage supply.

23

HVGND

High-Voltage NMOS FET Source. Connect to ground of the DC-DC boost circuit.

24

HVD

High-Voltage NMOS FET Drain. Connect to HVGND if unused.

—

EP

Exposed Pad. Connect to ground with a minimum of 9 vias for thermal conductivity improvement. It is

acceptable to use solder mask between the IC and the ground pad. It is not necessary to electrically

connect the exposed pad ground.

DS3923

High-Speed Current Mirror

with Sample/Hold Output

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Pin Description (continued)