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10

IRS233(0,2)(D)(S&J)PbF

Switching and Timing Relationships

The relationship between the input and output signals of the IRS233(0,2)(D) are illustrated below in Figures 3. From these

device.

LINx

(or HINx)

50%

50%

10%

10%

90%

90%

LOx

(or HOx)

Figure 3: Switching time waveforms

The following two figures illustrate the timing relationships of some of the functionality of the IRS233(0,2)(D); this functionality

is described in further detail later in this document.

During interval A of Figure 4, the HVIC has received the command to turn-on both the high- and low-side switches at the same

time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the high- and low-side output

are held in the off state.

Interval B of Figures 4 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a result, all of the

gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also held low) and a fault is

reported by the FAULT output transitioning to the low state. Once the ITRIP input has returned to the low state, the fault

condition is latched until the all LINx become high.