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ADC088S052 Datasheet(PDF) 5 Page - Texas Instruments |
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ADC088S052 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 25 page ADC088S052 www.ti.com SNAS340F – SEPTEMBER 2005 – REVISED MARCH 2013 ADC088S052 Converter Electrical Characteristics (1) (continued) The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, and CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits(2) Units POWER SUPPLY CHARACTERISTICS (CL = 10 pF) 2.7 V (min) VA, VD Analog and Digital Supply Voltages VA ≥ VD 5.25 V (max) VA = VD = +2.7V to +3.6V, 0.4 1.0 mA (max) fSAMPLE = 500 kSPS, fIN = 40 kHz Total Supply Current Normal Mode ( CS low) VA = VD = +4.75V to +5.25V, 1.3 1.7 mA (max) fSAMPLE = 500 kSPS, fIN = 40 kHz IA + ID VA = VD = +2.7V to +3.6V, 10 nA fSCLK = 0 ksps Total Supply Current Shutdown Mode (CS high) VA = VD = +4.75V to +5.25V, 30 nA fSCLK = 0 ksps VA = VD = +3.0V 1.2 3.0 mW (max) fSAMPLE = 500 kSPS, fIN = 40 kHz Power Consumption Normal Mode ( CS low) VA = VD = +5.0V 6.5 8.5 mW (max) fSAMPLE = 500 kSPS, fIN = 40 kHz PC VA = VD = +3.0V 0.03 µW fSCLK = 0 ksps Power Consumption Shutdown Mode (CS high) VA = VD = +5.0V 0.15 µW fSCLK = 0 ksps AC ELECTRICAL CHARACTERISTICS fSCLKMIN Minimum Clock Frequency 0.8 3.2 MHz (min) fSCLK Maximum Clock Frequency 16 8 MHz (max) 50 200 ksps (min) Sample Rate fS Continuous Mode 1000 500 ksps (max) tCONVERT Conversion (Hold) Time 13 SCLK cycles 30 40 % (min) DC SCLK Duty Cycle 70 60 % (max) tACQ Acquisition (Track) Time 3 SCLK cycles Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles tAD Aperture Delay 4 ns ADC088S052 Timing Specifications The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, and CL = 50pF. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits(1) Units tCSH CS Hold Time after SCLK Rising Edge 0 10 ns (min) CS Setup Time prior to SCLK Rising tCSS 5 10 ns (min) Edge tEN CS Falling Edge to DOUT enabled 5 30 ns (max) DOUT Access Time after SCLK Falling tDACC 17 27 ns (max) Edge DOUT Hold Time after SCLK Falling tDHLD 4 ns (typ) Edge DIN Setup Time prior to SCLK Rising tDS 3 10 ns (min) Edge tDH DIN Hold Time after SCLK Rising Edge 3 10 ns (min) tCH SCLK High Time 0.4 x tSCLK ns (min) tCL SCLK Low Time 0.4 x tSCLK ns (min) (1) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level). Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC088S052 |
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