InGaAs linear image sensor

G9201 to G9204 series

12

14

28

15

63.5 ± 0.15

53.3 ± 0.15

38.1 ± 0.15

35.6 ± 0.15

(28 ×) 2.54

(28 ×)

0.46

27.2 ± 0.15

INDEX MARK

NON-COOLED

ONE-STAGE TE-COOLED

4.35

1.8

AB

6.15

3.6

HAMAMATSU PHOTONICS K.K., Solid State Division

1126-1 Ichino-cho, Hamamatsu City, 435-8558 Japan, Telephone: (81) 053-434-3311, Fax: (81) 053-434-5184, http://www.hamamatsu.com

U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218

Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658

France: Hamamatsu Photonics France S.A.R.L.: 8, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10

United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777

North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01

Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741

Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions.

Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2003 Hamamatsu Photonics K.K.

Cat. No. KMIR1012E02

May 2003 DN

Terminal name

Input/Output

Function and recommended connection

CLK

Input

(CMOS logic compatible)

Clock pulse for operating the CMOS shift register

RESET

Input

(CMOS logic compatible)

Reset pulse for initializing the feedback capacitance in the charge amplifier

formed on the CMOS chip. The width of the reset pulse is integration time.

Vdd

Input

Supply voltage for operating the signal processing circuit on the CMOS chip.

Vss

-

Ground for the signal processing circuit on the CMOS chip.

INP

Input

Reset voltage for the charge amplifier array on the CMOS chip.

Cf SELECT

Input

Voltage that determines the feedback capacitance (Cf) on the CMOS chip.

Cf=10 pF at 0 V, and Cf=0.5 pF at 5 V.

CASE

-

This terminal is electrically connected to the package.

THERM

-

Thermistor for monitoring temperature inside the package. No connection for

room temperature operation type.

TE+, TE-

-

Power supply terminal for the thermoelectric cooler that cools the photodiode array.

No connection for room temperature operation type.

AD-TRIG

Output

Digital signal for AD conversion; positive polarity

VIDEO

Output

Analog video signal; positive polarity

Vref

Input

Reset voltage for the offset compensation circuit on the CMOS chip

s Dimensional outline (unit: mm)

KMIRA0010EA

KMIRC0013EA

s Pin connection (top view)

TE +

THERM

THERM

CASE

RESET

TE -

Vdd

Vss

INP

CLK

Vref

VIDEO

Cf SELECT

AD-TRIG

256 PIXELS

512 PIXELS

TE +

THERM

THERM

CASE

RESET-ODD

TE -

Vdd

Vss

INP

CLK-ODD

Vref

VIDEO-ODD

Cf SELECT

AD-TRIG-ODD

RESET-EVEN

AD-TRIG-EVEN

CLK-EVEN

VIDEO-EVEN

4