LV0221CS

No.A1823-5/6

Serial protocol

SDIO pin load / CL=20pF (The table below shows the design reference value.)

Parameter

Symbol

Min.

Typ.

Max.

Unit

SCL clock frequency Write

fSCL

0

10

MHz

SCL clock frequency Read

fSCL

0

4

MHz

SDIO data setup time

tDSU

50

ns

SDIO data hold time

tDHO

50

ns

SDIO output delay

tDDLY

10

80

ns

SEN “H” period

tENH

1.6

μs

SEN “L” period

tENL

200

ns

SCL rise time after SEN rise

tSTA

60

ns

SEN fall time after final SCL rise

tSTO

100

ns

Serial input “H” voltage

VIH

2.4

V

Serial input “L” voltage

VIL

0.6

V

SDIO output “H” voltage

VOH

2.5

2.9

3.3

V

SDIO output “L” voltage

VOL

0

0.3

0.8

V

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

1

2

3

4

5

6

78

9

10

11

12

13

14

15

16

MSB

LSB

MSB

LSB

Mode

Address

Data

(Output Data from Host)

(HOST) SEN

(HOST) SCLK

(HOST) SDIO

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

12

3

4

5

6

78

9

10

11

12

13

14

15

16

MSB

LSB

MSB

LSB

Mode

Address

Data

(Output Data from Host)

(HOST) SEN

(HOST) SCLK

(HOST) SDIO

SDIO

WRITE timing chart

READ timing chart

tSTA

tENH

(HOST) SEN

(HOST) SCLK

(HOST) SDIO

(HOST) SEN

(HOST) SCLK

(HOST) SDIO

SDIO

tENL

tSTO

tDSU

tDHO

tDDLY

WRITE

READ