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NCT75DR2G Datasheet(PDF) 11 Page - ON Semiconductor |
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NCT75DR2G Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 16 page NCT75 http://onsemi.com 11 Reading Data Reading data from the NCT75 is done in two different ways depending on the register being read. The configuration register is only 8 bits wide so a single byte read is used for this (shown in Figure 8). This consists of the device address followed by the data from the register. Reading the data in the temperature value register requires a two byte read (shown in Figure 9). This consists of the device address, followed by two bytes of data from the temperature register (the first byte is the MSB). In both cases the address pointer register of the register being read must be written to prior to performing a read operation. OS/ALERT Output Overtemperature Modes The OS/ALERT output pin can operate in two different modes – overtemperature mode and SMBus alert mode. The pin defaults to overtemperature mode on power up. This means that it becomes active when the measured temperature meets or exceeds the limit stored in the TOS setpoint register. At this point it can deal with the event in one of two ways which depends on the mode it is in. The two overtemperature modes are: comparator mode and interrupt mode. Comparator mode is the default mode on power up. More information on comparator and interrupt modes alsong with the SMBus alert mode are explained below. Comparator Mode In Comparator Mode, the OS/ALERT pin becomes active when the measured temperature equals or exceeds the limit stored in the TOS setpoint register. The pin returns to its inactive status when the temperature drops below the THYST setpoint register value. NOTE: Shutdown mode does not reset the output state for comparator mode. Interrupt Mode In the interrupt mode, the OS/ALERT pin becomes active when the temperature equals or exceeds the TOS limit for a consecutive number of faults. It can be reset by performing a read operation on any register in the NCT75. The output can only become active again when the TOS limit has been equalled or exceeded. Figure 11 shows how both the interrupt and comparator modes operate in relation to the output pin (OS/ALERT). It also shows the operation of the polarity bit in the configuration register. |
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