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ML7386 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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ML7386 Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
7 / 41 page FEDL7386B-07 ML7386/ML7386B 7/41 ●Miscellaneous Pin No Pin name I/O Active Level at reset Detail function 5 TCXO IA - I External clock (TCXO) input pin. *Fixed to GND level when crystal oscillator is used. 6 XO Oosc - O 26MHoecillator pin2 *Fixed to GND level when external clock generator is used 7 XIN Iosc - I 26MHz oscillator pin1 *Fixed to GND level when external clock generator is used 8 LD *1 O H L PLL Lock detect pin L: PLL unlock status H: PLL lock status 15 RSTN Is L I Hardware reset L: Rest, stop H: Normal operation 16 LP_CTLN I L I Sleep mode control pin L: Deep sleep mode H: Exit from deep sleep mode *1 Activated when write 0x18 to the [RF_MODE: 0x00] register. ●Power Supply Pin No Pin name I/O Active Level at reset Detail function 2 VDD_CP - - - Power supply pin for PLL charge pump block. (Connection for REG_OUT pin. Typ.1.5V) 17 VDD_IO - - - Power supply for digital IOs (Input voltage from 1.8 V to 3.3 V) 20 VDD_PA - - - Power supply pin for PA block. (Input voltage from 1.8V to 3.3V) 23 GND_PA - - - GND pin for PA block. 24 VDD_RF - - - Power supply pin for RF blocks. (Connection for REG_OUT pin. Typ.1.5V) 28 VDD_VCO - - - Power supply pin for VCO block. (Connection for REG_OUT pin. Typ.1.5V) |
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