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PE42556DI-Z Datasheet(PDF) 4 Page - Peregrine Semiconductor |
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PE42556DI-Z Datasheet(HTML) 4 Page - Peregrine Semiconductor |
4 / 9 page Page 4 of 9 ©2011-2012 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-50245-2 │ UltraCMOS® RFIC Solutions Product Brief PE42556 Visit psemi.com for full version of datasheet Power Handling Scaling with Frequency 0 5 10 15 20 25 30 1 10 100 1000 Freq (kHz) -12 -10 -8 -6 -4 -2 0 2 4 6 8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 Vdd (V) Upper Power Limit Figure 5 shows how the power limit in Figure 4 will increase with frequency. As the frequency increases, the contours and Maximum Power Limit Curve will increase with the increase in power handling shown on the curve. Figure 4. Maximum Operating Power Limit vs. Vdd and Input Power @ 9 kHz Figure 5. Operating Power Offset vs. Frequency (Normalized to 9 kHz) Figure 4 provides guidelines of how to adjust the Vdd and Input Power to the PE42556 device. The upper limit curve represents the maximum Input Power vs Vdd recommended for this part at low frequencies only. Please consult Table 3 for the 1 MHz ≤13.5 GHz range. To allow for sustained operation under any load VSWR condition, max power should be kept 6dB lower than max power in 50 Ohm. Power Handling Examples Example 1: Maximum power handling at 100 kHz, Z = 50 ohms, VSWR 1:1, and Vdd = 3V The power handling offset for 100 kHz from Fig. 5 is 7 dB The max power handling at Vdd = 3V is 5.5 dB from Fig. 4 Derate power under mismatch conditions Total maximum power handling for this example is 7 dB + 5.5 dB = 12.5 dBm Low Frequency Power Handling: ZL = 50Ω |
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