HD74AC373/HD74ACT373

3

Truth Table

Inputs

Outputs

OE

LE

D

n

O

n

HX

X

Z

LH

L

L

LH

H

H

L

LXO

0

H :

High Voltage Level

L

:

Low Voltage Level

Z

:

High Impedance

X :

Immaterial

O

Previous O

Functional Description

The HD74AC373/HD74ACT373 contains eight D-type latches with 3-state standard outputs. When the

Latch Enable (LE) input is High, data on the Dn inputs enters the latches. In this condition the latches are

transparent, i.e., a latch output will change state each time its D input changes. When LE is Low, the

latches store the information that was present on the D inputs setup time proceding the High-to-Low

transition of LE. The 3-state standard outputs are controlled by the Output Enable (

OE) input. When OE is

Low, the standard outputs are in the 2-state mode. When

OE is High, the standard outputs are in the high

impedance mode but this does not interfere with entering new data into the latches.

Logic Diagram

G

O

D

G

O

D

G

O

D

G

O

D

G

O

D

G

O

D

G

O

D

G

O

D

LE

OE

Please note that this diagram is provided only for the understanding of logic operations and should not be

used to estimate propagation delays.