HD74ALVC162835

18-bit Universal Bus Driver with 3-state Outputs

ADE-205-201E (Z)

Preliminary

6th. Edition

January 1999

Description

The HD74ALVC162835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V

Data flow from A to Y is controlled by the output enable (

OE). The device operates in the transparent mode

when the latch enable (LE) is high. When LE is low, the A data is latched if the clock (CLK) input is held

at a high or low logic level. If the LE is low, the A data is stored in the latch/flip flop on the low to high

transition of CLK. When

OE is high, the outputs are in the high impedance state.

To ensure the high impedance state during power up or power down,

OE should be tied to V

pullup registor; the minimum value of the registor is determined by the current sinking capability of the

driver.

All outputs, which are designed to sink up to 12 mA, include 26

Ω resistors to reduce overshoot and

undershoot.

Features

• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”

• V

• Typical V

• Typical V

• High output current ±12 mA (@V

• All outputs have equivalent 26 Ω series resistors, so no external resistors are required