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HV7351 Datasheet(PDF) 9 Page - Supertex, Inc |
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HV7351 Datasheet(HTML) 9 Page - Supertex, Inc |
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9 / 15 page  9 HV7351 Supertex inc. www.supertex.com Doc.# DSFP-HV7351 NR050213 Timing Diagram 1 TCk 0V 3.3V Trig Tx1 0V +70V Internal CLK (for N=2) 0V Example with Tx2 delay having two TCk cycles more than Tx1 TCk = 1.65V (0.5V LL) Tx2 Delay time set by Tx2 10 bit counter Delay time set by Tx1 10-bit counter t WTRIG needs to be at least 2 rising edges of TCk 0V 3.3V 0V 3.3V -70V +70V -70V 3.5 TCk cycles t WTRIG t SU-TRIG t dr1 t df2 t df1 t r1 t f2 t dr2 10%10% 90% 90% 10%10% 90% 90% t f1 t r2 Timing Diagram 2 Example with Tx2 delay having one TCk cycle more than Tx1 Delay time set by Tx2 10 bit counter 3.5 TCk cycles t SU-TRIG t WTRIG needs to be at least 2 rising edges of TCk t WTRIG Delay time set by Tx1 10-bit counter t df3 90% 10% 10% 90% t f3 t r3 t dr3 TCk 0V 3.3V Trig Tx1 0V +70V Internal CLk (for N=2) 0V TCk = 1.65V (0.5V LL) Tx2 0V 3.3V 0V 3.3V -70V +70V -70V |
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