11

HV633

Pin #

Function

Description

29

VDD (digital)*

Low-voltage digital supply voltage.

30

D7

Inputs for binary-format parallel data.

31

D6

32

D5

33

D4

34

D3

35

D2

36

D1

37

NC

No connect.

38

LVGND

This is ground for the logic section. HVGND and LVGND should be connected together

externally.

39

NC

No connect.

40

LC (Load Count)

Input for a pulse whose rising edge causes data from the input latches to enter the

comparator latches, and whose falling edge initiates the conversion of this binary data

to an output level (D-to-A). Also, the HV

initiated.

41

NC

No connect.

42

CC (Count Clock)

Input to the count clock generator whose increments are compared to the data in the

comparator latches.

43

CSO

Input pin for the chip select pulse (when DIR is low). Output pin for the chip select pulse

(when DIR is high).

44

NC

No connect.

45

VPP

This input biases the output source followers.

46

NC

No connect.

47

VR

High-voltage ramp input for charging the output stage hold capacitors (CH).This input

can be linear or non-linear as desired.

48

HVGND

This is ground for the high-voltage (output) section.HVGND and LVGND should be

connected together externally.

49

HV

High-voltage outputs

50

HV

51

HV

52

HV

53

HV

54

HV

55

HV

56

HV

57

HV

58

HV

* Analog VDD and digital VDD may be connected seperately for better noise immunity.