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HD74HCT137 Datasheet(PDF) 1 Page - Hitachi Semiconductor

Part # HD74HCT137
Description  3-to-8-line Decoder/Demultiplexer with Address Latch
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Manufacturer  HITACHI [Hitachi Semiconductor]
Direct Link  http://www.renesas.com/eng
Logo HITACHI - Hitachi Semiconductor

HD74HCT137 Datasheet(HTML) 1 Page - Hitachi Semiconductor

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HD74HCT137
3-to-8-line Decoder/Demultiplexer with Address Latch
Description
The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs.
When
GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the
latches. As long as
GL remains high no address changes will be recognized. Output enable controls, G
1
and G
2, control the state of the outputs independently of the select or latch-enable inputs.
All of the outputs are high unless G
1 is high and G2 is low.
The HD74HCT137 is ideally suited for the
implementation of glitchfree decoders in stored-address applications in bus oriented systems.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: t
pd (A, B, C to Y) = 18 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V
CC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I
CC (static) = 4 µA max (Ta = 25°C)


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