HM62G36256 Series

3

Pin Description

Name

I/O type

Descriptions

Notes

V

DD

Supply

Core power supply

V

SS

Supply

Ground

V

DDQ

Supply

Output power supply

V

REF

Supply

Input reference: provides input reference voltage

K

Input

Clock input. Active high.

K

Input

Clock input. Active low.

SS

Input

Synchronous chip select

SWE

Input

Synchronous write enable

SAn

Input

Synchronous address input

n = 0, 1, 2...17

SWEx

Input

Synchronous byte write enables

x = a, b, c, d

G

Input

Asynchronous output enable

ZZ

Input

Power down mode select

ZQ

Input

Output impedance control

1

DQxn

I/O

Synchronous data input/output

x = a, b, c, d

n = 0, 1, 2...8

M1, M2

Input

Output protocol mode select

TMS

Input

Boundary scan test mode select

TCK

Input

Boundary scan test clock

TDI

Input

Boundary scan test data input

TDO

Output

Boundary scan test data output

NC

—

No connection

M1

M2

Protocol

Notes

V

SS

V

DD

Synchronous register to register operation

2

Notes: 1. ZQ is to be connected to V

open, output buffer impedance will be maximum. A case of minimum impedance, it needs to

connect over 120

Ω between ZQ and V

2. There is 1 protocol with mode pin. Mode control pins (M1, M2) are to be tied either V

respectively. The state of the Mode control inputs must be set before power-up and must not

change during device operation. Mode control inputs are not standard inputs and may not meet

V

This SRAM is tested only in the synchronous register to register

operation.