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HN58V65A Datasheet(PDF) 8 Page - Hitachi Semiconductor |
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HN58V65A Datasheet(HTML) 8 Page - Hitachi Semiconductor |
8 / 27 page HN58V65A Series, HN58V66A Series Write Cycle 1 (V CC = 2.7 to 4.5 V) Parameter Symbol Min* 3 Typ Max Unit Test conditions Address setup time t AS 0 ——ns Address hold time t AH 50 ——ns CE to write setup time (WE controlled) t CS 0 ——ns CE hold time (WE controlled) t CH 0 ——ns WE to write setup time (CE controlled) t WS 0 ——ns WE hold time (CE controlled) t WH 0 ——ns OE to write setup time t OES 0 ——ns OE hold time t OEH 0 ——ns Data setup time t DS 50 ——ns Data hold time t DH 0 ——ns WE pulse width (WE controlled) t WP 200 — — ns CE pulse width (CE controlled) t CW 200 — — ns Data latch time t DL 100 — — ns Byte load cycle t BLC 0.3 — 30 µs Byte load window t BL 100 — — µs Write cycle time t WC — — 10* 4 ms Time to device busy t DB 120 — — ns Write start time t DW 0* 5 ——ns Reset protect time* 2 t RP 100 — — µs Reset high time* 2, 6 t RES 1— — µs Notes: 1. t DF and t DFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. This function is supported by only the HN58V66A series. 3. Use this device in longer cycle than this value. 4. t WC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically completes the internal write operation within this value. 5. Next read or write operation can be initiated after t DW if polling techniques or RDY/Busy are used. 6. This parameter is sampled and not 100% tested. 7. A6 through A12 are page addresses and these addresses are latched at the first falling edge of WE. 8. A6 through A12 are page addresses and these addresses are latched at the first falling edge of CE. 9. See AC read characteristics. |
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