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HN58V1001T-25 Datasheet(PDF) 1 Page - Hitachi Semiconductor |
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HN58V1001T-25 Datasheet(HTML) 1 Page - Hitachi Semiconductor |
1 / 22 page HN58V1001 Series 1M EEPROM (128-kword × 8-bit) Ready/ Busy and RES function ADE-203-314G (Z) Rev. 7.0 Oct. 31, 1997 Description The Hitachi HN58V1001 is a electrically erasable and programmable ROM organized as 131072-word × 8- bit. It has realized high speed, low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. It also has a 128-byte page programming function to make the write operations faster. Features • Single 3 V supply: 2.7 V to 5.5 V • Access time: 250 ns (max) • Power dissipation Active: 20 mW/MHz, (typ) Standby: 110 µW (max) • On-chip latches: address, data, CE, OE, WE • Automatic byte write: 15 ms (max) • Automatic page write (128 bytes): 15 ms (max) • Data polling and RDY/Busy • Data protection circuit on power on/off • Conforms to JEDEC byte-wide standard • Reliable CMOS with MNOS cell technology • 104 erase/write cycles (in page mode) • 10 years data retention • Software data protection • Write protection by RES pin |
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