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HTG2150 Datasheet(PDF) 10 Page - Holtek Semiconductor Inc |
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HTG2150 Datasheet(HTML) 10 Page - Holtek Semiconductor Inc |
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10 / 49 page  HTG2150 10 July 24, 2000 Preliminary grammer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent eight return address are stored). Data memory - RAM · Bank 0 (BP4~BP0=00000) The Bank 0 data memory includes special purpose and general purpose memory. The special purpose memory is addressed from 00H to 2FH, while general purpose memory is addressed from 40H to FFH. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Ex- cept for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through the memory pointer registers (MP0;01H, MP1;03H). · Bank 15 (BP4~BP0=01111B) The range of RAM starts from 80H to A7H. On the LCD, every bit stands for one dot. If the bit is ²1², the light of the dot on the LCD will be turned on. If the bit is ²0², then it will be turned off. Only MP1 can deal with the memory of this range. The contrast form of RAM location, COM- MON, and SEGMENT is as follows. Indirect addressing register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] ac- cess data memory are pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly will return the result 00H. Writing indirectly results in no operation. The function of data movement between two indi- rect addressing registers, is not supported. The memory pointer registers, MP0 and MP1, are 8-bit registers which can be used to access the data memory by combining corresponding indi- rect addressing registers but Bank 15 can use MP1 only. Accumulator The accumulator is closely related to ALU oper- ations. It is also mapped to location 05H of the data memory and it can carry out immediate data operations. The data movement between two data memories has to pass through the ac- cumulator. 3F H FFH TM R 2 TM R 2 C IN T C H TB H P TM R 3 TM R 3 C PW M C PW M CO M R X' T A L C 40H 1D H 1E H 1F H 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2A H 2B H 2C H 2D H 2E H 2F H 30H LC D C LC D C ont r o l R egi s t er C o m m on P ad A ddr es s R o t a t o r R ead a s " 00" P B b i t 3 / 2 / 1 / 0 R ead= 0 : U n u s e d 80H A7 H B ank 15 D a t a M em or y ( 40 B y t e ) G ene r a l P u r pos e B ank 0 D at a M e m o r y ( 192 B y t e ) 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0A H 0B H 0C H 0D H 0E H 0F H 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1A H 1B H 1C H IA R 0 MP 0 IA R 1 MP 1 BP AC C PC L TB L P TB L H WD T S ST AT U S IN T C TM R 0 H TM R 0 L TM R 0 C PA PA C PB PB C P A I / O D at a R egi s t er P A I / O C ont r o l R egi s t e r P B I / O D at a R egi s t er P B I / O C ont r o l R egi s t e r I ndi r e c t A ddr es s i ng R egi s t er 0 M e m o r y P oi nt er 0 I ndi r e c t A ddr es s i ng R egi s t er 1 M e m o r y P oi nt er 1 B ank P oi nt er A ccu m u l a t o r P r ogr am C ount er Low er - b y t e R egi s t er T a bl e P o i n t e r Low er - o r d er B y t e R e gi s t er T a bl e H i gher - o r der B y t e R egi s t er W a t c hd og T i m e r O pt i on S e t t i n g R egi s t er S t at us R eg i s t e r I n t e r r upt C on t r ol R eg i s t e r T i m e r C o unt er 0 H i gher - o r der B y t e R egi s t er T i m e r C o unt er 0 L o w er - o r der B y t e R egi s t e r T i m e r C o unt er 0 C ont r o l R egi s t e r S pe c ia l P u r po s e D a t a M em or y I n t e r r upt C on t r ol H i ghe r - or der B y t e R egi s t e r T a bl e P o i n t e r H i gh er - o r d e r B y t e R e g i s t er T i m e r 2 R egi s t er T i m e r 2 C ont r o l R egi s t er T i m e r 3 R egi s t er T i m e r 3 C ont r o l R egi s t er X ' t a l F a st O sci l l a t o r u p C o n t r o l P W M C ont r o l PW M D a t a RAM mapping |
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