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HI-8588PDT-10 Datasheet(PDF) 1 Page - Holt Integrated Circuits |
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HI-8588PDT-10 Datasheet(HTML) 1 Page - Holt Integrated Circuits |
1 / 6 page HI-8588-10 ARINC 429 LINE RECEIVER DESCRIPTION FEATURES PIN CONFIGURATION SUPPLY VOLTAGES FUNCTION TABLE RINA GND ROUTA ROUTB TESTB TESTA VCC RINB 2 3 4 5 6 7 8 1 vcc = 5.0V± 5% PIN SYMBOL FUNCTION DESCRIPTION VCC SUPPLY 5 VOLT SUPPLY TESTA LOGIC INPUT CMOS RINB ARINC INPUT RECEIVERB INPUT RINA ARINC INPUT RECEIVERA INPUT GND POWER GROUND ROUTA LOGIC OUTPUT RECEIVER CMOS OUTPUT A ROUTB LOGIC OUTPUT RECEIVER CMOS OUTPUT B TESTB LOGIC INPUT CMOS PIN DESCRIPTION TABLE The HI-8588-10 ARINC 429 bus interface receiver is simi- lar to the HI-8588 with the exception that it allows an exter- nal 10 Kohm resistor in series with each ARINC input with- out affecting the ARINC input thresholds. The product is especially useful in applications where lightning protection circuitry is also required. In addition, the test inputs force both of the outputs to zero instead open circuit. The ana- log/digital CMOS product requires onlya5 volt supply and is available ina SO8 pin package. Each side of the ARINC bus be connected through a 10 Kohm series resistor in order for the chip to detect the correct ARINC levels. The typical 10 volt differential signal is translated and input toa window comparator and latch. The comparator levels are set so that with the external 10 Kohm resistors they are just below the standard 6.5 volt minimum ARINC data threshold and just above the stan- dard 2.5 voltmaximum ARINC null threshold. The TESTA and TESTB inputs bypass the analog inputs for testing purposes. Also if TESTA and TESTB are both taken high, the digital outputs are forced to zero. must January 2001 (DS8588-10 Rev. A) 01/01 HOLT INTEGRATED CIRCUITS 1 |
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