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HI-8588PST Datasheet(PDF) 2 Page - Holt Integrated Circuits |
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HI-8588PST Datasheet(HTML) 2 Page - Holt Integrated Circuits |
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2 / 6 page  HI-8588 FUNCTIONAL DESCRIPTION RINA RINB NULL ZERO NULL ONE TEST TESTA TEST TEST TESTB TESTA ' TESTB ROUTB TESTA ' TESTB ROUTA FIGURE 1- RECEIVER BLOCK DIAGRAM TEST R S Q R LATCH S Q LATCH ESD PROTECTION AND TRANSLATION 1 2 8 6 7 4 3 4 5 6 7 2 3 FIGURE 2- APPLICATION DIAGRAM APPLICATION INFORMATION 8 5 1 RECEIVER Figure1 shows the general architecture of the ARINC 429 receiver. The receiver operates off the VCC supply only. The inputs RINA and RINB each have series resistors, typi- cally 35K ohms. They connect to level translators whose resistance to Ground is typically 10K ohms. Therefore, any series resistance added to the inputs will affect the voltage translation. After level translation, the inputs are buffered and become inputs toa differential amplifier. The amplitude of the dif- ferential signal is compared to levels derived from a di- vider between VCC and Ground. The nominal settings cor- respond toa One/Zero amplitude of 6.0V anda Null ampli- tude of 3.3V. The status of the ARINC receiver input is latched. A Null input resets the latches anda One or Zero input sets the latches. The logic at the output is controlled by the test signal which is generated by the logical OR of theTestA and TestB pins. If TestA and TestB are both One, then the re- ceiver is powered down and the output pins float. The powerdown does not disconnect the internal resistors at the ARINC input. Figure2 showsa possible application of the HI-8588 interfacing an ARINC receive channel to the HI-6010 which in turn interfaces to an 8-bit bus. HOLT INTEGRATED CIRCUITS 2 |
Similar Part No. - HI-8588PST |
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Similar Description - HI-8588PST |
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