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HI-8683PDI Datasheet(PDF) 3 Page - Holt Integrated Circuits |
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HI-8683PDI Datasheet(HTML) 3 Page - Holt Integrated Circuits |
3 / 10 page HI-8683, HI-8684 HOLT INTEGRATED CIRCUITS 3 PROTOCOL DETECTION ARINC clock and data in the HI-8683 are derived from the two streams of digital data at the INA and INB inputs and the resulting One/Zero data is shifted intoa 32-bit input register as illustrated in Figure 3. In the HI-8684, the One/Zero data shifted into the input reg- ister is created from either the two digital outputs of the built- in line receiver (Figure 3) or the TESTA and TESTB inputs (Figure 4). For ARINC 561 operation, the INA and INB data streams in- puts must be derived from the ARINC 561 data, clock and sync with external logic. GAP DETECTION The end ofa data word is detected by an internal counter that times out whena data One or Zero is not received for a period equal to 16 cycles of the GAPCLK signal. The gap detection time may vary between 16 and 17 cycles of the GAPCLK signal since the incoming data and GAPCLK are not usually synchronous inputs. The required frequency of GAPCLK isa function of the mininum gap time specified for the type of ARINC data being received. Table1 indicates typical frequencies that may be used for the various data rates normally encountered. BIT COUNT PARITY DETECT GAP DETECT 32-BIT SHIFT REG. 32-BIT RECEIVE BUFFER 32-BIT TO 8-BIT MUX ERROR DETECT CLOCK & DATA DETECT HI-8683 ONLY HI-8684 ONLY INA PARITY ENB INB RINB TESTA TESTB GAPCLK RESET BYTE COUNT READ DATA RDY ERROR 32 8 32 Figure 1. Block Diagram ESD PROTECTION & LINE RECEIVER ESD PROTECTION DATABUS BIT PERIOD MINIMUM GAP GAP CLOCK GAP DETECTION TYPE ( s) ( s) MHz TIME ( s) µ µ µ 429 10 45 0.75 21.3- 22.7 1.0 16- 17 1.5 10.7- 11.3 429 69 - 133 310- 599 0.1 160- 170 575 69 - 133 310- 599 0.1 160- 170 561 69 - 133 103- 200 0.2 80- 85 Table1- Typical Gap Detection Times FUNCTIONAL DESCRIPTION (cont.) RXA RXB 10K Ω BIT 32 BIT 32 RINA D0- D7 DATA CLK RINB-10 RINA-10 10K Ω 25K Ω 25K Ω |
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