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AT32AP7001 Datasheet(PDF) 2 Page - ATMEL Corporation |
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AT32AP7001 Datasheet(HTML) 2 Page - ATMEL Corporation |
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2 / 49 page  2 32015GS–AVR32–09/09 AT32AP7001 1. Part Description The AT32AP7001 is a complete System-on-chip application processor with an AVR32 RISC processor achieving 210 DMIPS running at 150 MHz. AVR32 is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular empha- sis on low power consumption, high code density and high application performance. AT32AP7001 implements a Memory Management Unit (MMU) and a flexible interrupt controller supporting modern operating systems and real-time operating systems. The processor also includes a rich set of DSP and SIMD instructions, specially designed for multimedia and telecom applications. AT32AP7001 incorporates SRAM memories on-chip for fast and secure access. For applica- tions requiring additional memory, external 16-bit SRAM is accessible. Additionally, an SDRAM controller provides off-chip volatile memory access as well as controllers for all industry standard off-chip non-volatile memories, like Compact Flash, Multi Media Card (MMC), Secure Digital (SD)-card, SmartCard, NAND Flash and Atmel DataFlash™. The Direct Memory Access controller for all the serial peripherals enables data transfer between memories without processor intervention. This reduces the processor overhead when transfer- ring continuous and large data streams between modules in the MCU. The Timer/Counters includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measure- ment, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. A pixel co-processor provides color space conversions for images and video, in addition to a wide variety of hardware filter support Synchronous Serial Controllers provide easy access to serial communication protocols, audio standards like I2S and frame-based protocols. The Java hardware acceleration implementation in AVR32 allows for a very high-speed Java byte-code execution. AVR32 implements Java instructions in hardware, reusing the existing RISC data path, which allows for a near-zero hardware overhead and cost with a very high performance. The Image Sensor Interface supports cameras with up to 12-bit data buses. PS2 connectivity is provided for standard input devices like mice and keyboards. AT32AP7001 integrates a class 3 Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. The C-compiler is closely linked to the architecture and is able to utilize code optimization fea- tures, both for size and speed. |
Similar Part No. - AT32AP7001_14 |
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Similar Description - AT32AP7001_14 |
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