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HI-8684PST Datasheet(PDF) 2 Page - Holt Integrated Circuits |
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HI-8684PST Datasheet(HTML) 2 Page - Holt Integrated Circuits |
2 / 10 page HI-8683, HI-8684 PIN DESCRIPTIONS DATA RDY OUTPUT Receiver data ready flag.A high level indicates data is available in the receive buffer. Flag goes low when the first 8-bit byte is read. D1 to D7 OUTPUT 8-bit parallel data bus (tri-state) GND POWER 0V INPUT Read strobe. A low level transfers receive buffer data to the data bus PARITY ENB INPUT Parity Enable-A high level activates odd parity checking which replaces the 32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged ERROR OUTPUT Error Flag. A high level indicatesa bit count error (number of ARINC bits was less than or greater than 32) and/ora parity error if parity detection was enabled (PARITY ENB high) INA INPUT Positive digital serial data input (HI-8683 only) INB INPUT Negative digital serial data input (HI-8683 only) RINA/RINA-10 INPUT Positive direct ARINC serial data input RINB/RINB-10 INPUT Negative direct ARINC serial data input (HI-8684& HI-8684-10 only) INPUT Internal logic states are initialized witha low level TESTA INPUT Used in conjunction with the TESTB input to bypass the built-in analog line receiver circuitry TESTB INPUT U GAPCLK INPUT Gap Clock. Determines the minimum time required between ARINC words for detection. The minimum word gap time is between 16 and 17 clock cycles of this signal. Vcc POWER +5V ±10% supply SIGNAL FUNCTION DESCRIPTION READ RESET (HI-8684& HI-8684-10 only) (HI-8684& HI-8684-10 only) sed in conjunction with the TESTA input to bypass the built-in analog line receiver circuitry (HI-8684& HI-8684-10 only) HOLT INTEGRATED CIRCUITS 2 FUNCTIONAL DESCRIPTION The HI-8683 and HI-8684 are serial to 8-bit parallel convert- ers. The incoming data stream is serially shifted into an input register, checked for errors, and then transferred in parallel to a 32-bit receive buffer. The receive data can be accessed us- ing four 8-bit parallel read operations while the next serial data steam is being received. Figure1 isa block diagram of both the HI-8683 and HI-8684. The difference between the two products is the HI-8684 has a built-in line receiver whereas the HI-8683 is strictlya digital device and requires an external ARINC line receiver such as the Holt HI-8482, HI-8588 or HI-8590 to interface to the ARINC 429 bus. RECEIVER INPUTS HI-8684 Line Receiver Typically 35K resistors are in series with both the RINA and RINB ARINC 429 inputs. They connect to level translators whose resistance to GND is typically 10K After level trans- lation, the buffered inputs drivea differential amplifier. The differential signal is compared to levels derived froma divider between VCC and GND. The nominal settings correspond to a One/Zero amplitude of 6.0V anda Null amplitude of 3.3V. A valid ARINC One/Zero input setsa latch and a Null input re- sets the latch. Since any added external series resistance will affect the volt- age translation, the HI-8684-10 is available with 25K of the 35K series resistance required for proper ARINC 429 level detection. The remaining 10K required that must be added can be incorporated in other external circuitry such as light- ning protection. Except for the different input series resis- tance, the HI-8684 and HI-8684-10 are identical. Ω Ω. Ω Ω Ω |
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