AN-6099

APPLICATION NOTE

© 2013 Fairchild Semiconductor Corporation

www.fairchildsemi.com

Rev. 1.0.1 • 3/12/13

2

The low- and medium-voltage MOSFETs developed rapidly

to accomplish significant performance improvements with

trench gate technology after the introduction of planar

technology in early 1970s. The trench gate MOSFETs are

now the preferred power devices for medium- to low-

voltage power applications. These MOSFETs implement a

gate structure embedded into a trench region carefully

etched into the device structure. The specific on-resistance

improves about 30% with this new technology, thanks to the

ability to increase channel density and eliminate the JFET

resistance

component.

Power

losses

in

synchronous

rectification can be lowered when the product of MOSFET

on resistance and drain current is less than the diode

forward-voltage drop. However, low on-resistance is not the

only requirement for the power switches in terms of

synchronous rectification. They should have small gate

charge to reduce driving losses. Soft-body diode reverse-

recovery characteristics can reduce snubber losses by

damping the peak level of voltage spikes. There are also

system efficiency of synchronous rectification. Fairchild

designed a new highly optimized power MOSFET, called

PowerTrench

synchronous rectification with deep analysis of power losses

in synchronous rectification of server power supplies or

telecom rectifiers.

Medium Voltage MOSFETs

Technologies

considered the single most-important indicator of MOSFET

performance in switching mode power supplies. Therefore,

several new technologies have been developed to improve

cell structure have dramatically changed through the years,

the vertical cell structure of a MOSFET can be classified

into three structure types: planar, trench, or lateral. Among

the three structures, trench-gated MOSFETs have become

the mainstream for high-performance discrete power

Voltage Ratings

They are chosen primarily for their particularly low specific

as shown in Figure 2. With compelling advantage of the

the shortest possible current path (vertical) from drain to

source, it is possible to increase cell density without any

JFET pinch-off effect. The percentage of resistance

associated with each region varies dramatically, depending

low conduction losses, consideration must be made for

enhanced FOM, where trade-offs in trench depths and

widths exist to optimize the structure.

Source

N+ Substrate

N- Epi Layer

P

P

+

N

+

Metal

Drain

Gate

Poly

Oxide

Drift Region

A

B

E-field

A

B

BV

Figure 3. Conventional Trench Gate MOSFET

Drain

Source

N+ Substrate

P

P

+

N

+

Metal

Poly

Gate

N- Epi Layer

Oxide

Shield

Poly

E-field

A

BV

Figure 4. The latest trench MOSFET with shielded gate

technology

Variations to the standard trench cell are often designed

with the intention of preserving low resistance, while

enhancing the FOM. The conventional trench gate structure

of Figure 3 enables lower on resistance by increasing the