8

AT24C512SC

1933B–SEEPR–04/04

Device Addressing

The 512K EEPROM requires an 8-bit device address word following a start condition to

enable the chip for a read or write operation (see Figure 8). The device address word

consists of a mandatory “one, zero” sequence for the first four most significant bits as

shown. This is common to all two-wire EEPROM devices.

The next three bits of the device address word are unused. These three unused bits

should be set to “0”.

The eighth bit of the device address is the read/write operation select bit. A read opera-

tion is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a “0”. If a compare is

not made, the device will return to a standby state.

Figure 8. Device Address

Write Operations

BYTE WRITE: A write operation requires two 8-bit data word addresses following the

device address word and acknowledgment. Upon receipt of this address, the EEPROM

will again respond with a “0” and then clock in the first 8-bit data word. Following receipt

of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a

microcontroller, then must terminate the write sequence with a stop condition. At this

All inputs are disabled during this write cycle and the EEPROM will not respond until the

write is complete (see Figure 9).

Figure 9. Byte Write

MSB

LSB

1

0

100

0

0

R/W