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AT89LP51RD2 Datasheet(PDF) 3 Page - ATMEL Corporation |
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AT89LP51RD2 Datasheet(HTML) 3 Page - ATMEL Corporation |
3 / 26 page 3 3714AS–MICRO–7/11 AT89LP51RD2/ED2/ID2 Summary - Preliminary 1.5 Pin Description Table 1-1. Atmel AT89LP51RD2/ED2/ID2 Pin Description Pin Number Symbol Type Description VQFP VQFN PLCC (1) PDIP 176 P1.5 I/O I/O I/O I/O P1.5: User-configurable I/O Port 1 bit 5. MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When configured as slave, this pin is an output. MOSI: SPI master-out/slave-in (Remap mode). When configured as master, this pin is an output. When configured as slave, this pin is an input. During In-System Programming, this pin is an input. CEX2: Capture/Compare external I/O for PCA module 2. 2 8 7P1.6 I/O I/O I/O I/O P1.6: User-configurable I/O Port 1 bit 6. SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is an input. MISO: SPI master-in/slave-out (Remap mode). When configured as master, this pin is an input. When configured as slave, this pin is an output. During In-System Programming, this pin is an output. CEX3: Capture/Compare external I/O for PCA module 3. 39 8 P1.7 I/O I/O I/O I/O P1.7: User-configurable I/O Port 1 bit 7. MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as slave, this pin is an input. SCK: SPI Clock (Remap mode). When configured as master, this pin is an output. When configured as slave, this pin is an input. During In-System Programming, this pin is an input. CEX4: Capture/Compare external I/O for PCA module 4. 4109 RST I/O I RST: External Reset input (Reset polarity depends on POL pin). The RST pin can output a pulse when the internal Watchdog reset or POR is active. DCL: Serial Debug Clock input for On-Chip Debug Interface when OCD is enabled. 511 10 P3.0 I/O I P3.0: User-configurable I/O Port 3 bit 0. RXD: Serial Port Receiver Input. 612 P4.1 I/O I/O P4.1: User-configurable I/O Port 4bit 1. SDA: TWI bidirectional Serial Data line. 713 11 P3.1 I/O O P3.1: User-configurable I/O Port 3 bit 1. TXD: Serial Port Transmitter Output. 8 14 12 P3.2 I/O I P3.2: User-configurable I/O Port 3 bit 2. INT0: External Interrupt 0 Input or Timer 0 Gate Input. 915 13 P3.3 I/O I P3.3: User-configurable I/O Port 3 bit 3. INT1: External Interrupt 1 Input or Timer 1 Gate Input 10 16 14 P3.4 I/O I/O P3.4: User-configurable I/O Port 3 bit 4. T1: Timer/Counter 0 External input or output. 11 17 15 P3.5 I/O I/O P3.5: User-configurable I/O Port 3 bit 5. T1: Timer/Counter 1 External input or output. 12 18 16 P3.6 I/O O P3.6: User-configurable I/O Port 3 bit 6. WR: External memory interface Write Strobe (active-low). 13 19 17 P3.7 I/O O P3.7: User-configurable I/O Port 3 bit 7. RD: External memory interface Read Strobe (active-low). 14 20 18 P4.7 I/O O P4.7: User-configurable I/O Port 4 bit 7. XTAL2A: Output from inverting oscillator amplifier A. It may be used as a port pin if the internal RC oscillator or external clock is selected as the clock source A. 15 21 19 P4.6 I/O I P4.6: User-configurable I/O Port 4 bit 6. XTAL1A: Input to the inverting oscillator amplifier A and internal clock generation circuits. It may be used as a port pin if the internal RC oscillator is selected as the clock source A. |
Similar Part No. - AT89LP51RD2_14 |
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