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ATTINY10 Datasheet(PDF) 6 Page - ATMEL Corporation |
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ATTINY10 Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 170 page  6 ATtiny4/5/9/10 [DATASHEET] 8127F–AVR–02/2013 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure cor- rect program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1. Block Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System reprogrammable Flash memory. The fast-access Register File contains 16 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two oper- ands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 16 x 8 General Purpose Registrers ALU Status and Control I/O Lines Data Bus 8-bit Data SRAM Interrupt Unit Watchdog Timer Analog Comparator Timer/Counter 0 ADC |
Similar Part No. - ATTINY10_14 |
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Similar Description - ATTINY10_14 |
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