11

ATA6831C [DATASHEET]

9251D–AUTO–11/12

4.13

Low-side open load

detection current

Input register bit 13

(OLD) = low, output off

2, 12, 15

–6

–9

–11

mA

A

4.13a

Low-side open load

detection threshold

level

Input register bit 13

(OLD) = low, output off

0.5

1.5

2.5

V

A

4.14

Open load detection

current ratio

2

3

4

4.15

High-side output switch

20

µs

A

4.16

Low-side output switch

20

µs

A

4.17

High-side output switch

20

µs

A

4.18

Low-side output switch

3

µs

A

4.19

Dead time between

corresponding

high-side and low-side

switches

1

µs

A

4.20

20

µs

A

4.21

-5

5

µs

A

5

Logic Inputs DI, CLK, CS, PWM

5.1

Input voltage low-level

threshold

3, 4, 5, 6

0.3

×

V

A

5.2

Input voltage high-level

threshold

3, 4, 5, 6

0.7

×

V

A

5.3

Hysteresis of input

voltage

3, 4, 5, 6

50

700

mV

A

5.4

Pull-down current

pins DI, CLK, PWM

4, 5, 6

10

65

µA

A

5.5

Pull-up current

pin CS

3

–65

–10

µA

A

8.

Electrical Characteristics (Continued)

No.

Parameters

Test Conditions

Pin

Symbol

Min.

Typ.

Max.

Unit

Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90%

of final level. Device not in standby for t > 1ms.

2.

Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.

3.

Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.