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ATA6831C Datasheet(PDF) 11 Page - ATMEL Corporation |
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ATA6831C Datasheet(HTML) 11 Page - ATMEL Corporation |
11 / 17 page 11 ATA6831C [DATASHEET] 9251D–AUTO–11/12 4.13 Low-side open load detection current Input register bit 13 (OLD) = low, output off VVS = 13V, VOut 1-3 = 13V 2, 12, 15 IOut1-3L –6 –9 –11 mA A 4.13a Low-side open load detection threshold level Input register bit 13 (OLD) = low, output off VVS = 13V, IOut1-3 =0mA 2, 12, 15 VOut1-3_OLD_LTh 0.5 1.5 2.5 V A 4.14 Open load detection current ratio IOut1-3L/IOut1-3H 2 3 4 4.15 High-side output switch on delay(1),(2) VVS = 13V RLoad =30Ω tdon 20 µs A 4.16 Low-side output switch on delay(1),(2) VVS = 13V RLoad =30Ω tdon 20 µs A 4.17 High-side output switch off delay(1),(2) VVS =13V RLoad = 30Ω tdoff 20 µs A 4.18 Low-side output switch off delay(1),(2) VVS =13V RLoad = 30Ω tdoff 3 µs A 4.19 Dead time between corresponding high-side and low-side switches VVS =13V RLoad = 30Ω tdon – tdoff 1 µs A 4.20 ΔtdPWM low-side switch(3) VVS = 13V RLoad = 30Ω ΔtdPWM = tdon – tdoff 20 µs A 4.21 ΔtdPWM high-side switch(3) VVS = 13V RLoad = 30Ω ΔtdPWM = tdon – tdoff -5 5 µs A 5 Logic Inputs DI, CLK, CS, PWM 5.1 Input voltage low-level threshold 3, 4, 5, 6 VIL 0.3 × VVCC V A 5.2 Input voltage high-level threshold 3, 4, 5, 6 VIH 0.7 × VVCC V A 5.3 Hysteresis of input voltage 3, 4, 5, 6 ΔVI 50 700 mV A 5.4 Pull-down current pins DI, CLK, PWM VDI, VCLK, VPWM = VVCC 4, 5, 6 IPD 10 65 µA A 5.5 Pull-up current pin CS VCS = 0V 3 IPU –65 –10 µA A 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.75V < VVCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. |
Similar Part No. - ATA6831C_14 |
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Similar Description - ATA6831C_14 |
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