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ATF1508AS(L)

0784P–PLD–7/05

Description

The ATF1508AS is a high-performance, high-density complex programmable logic device

(CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 128 logic macrocells

and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic

PLDs. The ATF1508AS’s enhanced routing switch matrices increase usable gate count and

increase odds of successful pin-locked design modifications.

The ATF1508AS has up to 96 bi-directional I/O pins and four dedicated input pins, depending

on the type of device package selected. Each dedicated pin can also serve as a global control

signal, register clock, register reset or output enable. Each of these control signals can be

selected for use individually within each macrocell.

Each of the 128 macrocells generates a buried feedback that goes to the global bus. Each

input and I/O pin also feeds into the global bus. The switch matrix in each logic block then

selects 40 individual signals from the global bus. Each macrocell also generates a foldback

logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1508AS

allows fast, efficient generation of complex logic functions. The ATF1508AS contains eight

such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product

terms.

The ATF1508AS macrocell, shown in Figure 1, is flexible enough to support highly-complex

logic functions operating at high speed. The macrocell consists of five sections: product terms

and product term select multiplexer; OR/XOR/CASCADE logic, a flip-flop, output select and

enable, and logic array inputs.

Unused macrocells are automatically disabled by the compiler to decrease power consump-

tion. A security fuse, when programmed, protects the contents of the ATF1508AS. Two bytes

(16 bits) of User Signature are accessible to the user for purposes such as storing project

name, part number, revision or date. The User Signature is accessible regardless of the state

of the security fuse.

The ATF1508AS device is an in-system programmable (ISP) device. It uses the industry-stan-

dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-

scan Description Language (BSDL). ISP allows the device to be programmed without remov-

ing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also

allows design modifications to be made in the field via software.

Product Terms and

Select Mux

Each ATF1508AS macrocell has five product terms. Each product term receives as its inputs

all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as needed to

the macrocell logic gates and control signals. The PTMUX programming is determined by the

design compiler, which selects the optimum macrocell configuration.

OR/XOR/

CASCADE Logic

The ATF1508AS’s logic structure is designed to efficiently support all types of logic. Within a

single macrocell, all the product terms can be routed to the OR gate, creating a 5-input

AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be

expanded to as many as 40 product terms with a little small additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-

tions. One input to the XOR comes from the OR sum term. The other XOR input can be a

product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input

allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimiza-

tion of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.