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AT17F32 Datasheet(PDF) 3 Page - ATMEL Corporation |
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AT17F32 Datasheet(HTML) 3 Page - ATMEL Corporation |
3 / 14 page 3 3393C–CNFG–6/05 AT17F32 3. Block Diagram 4. Device Description The control signals for the configuration memory device (CE, RESET/OE, and CLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configura- tion process and retrieve data from the configuration device without requiring an external intelligent controller. The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F Series Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. Config. Page Select Power-on Reset Flash Memory Clock/Oscillator Logic 2-wire Serial Programming Serial Download Logic Control Logic CLK CEO(A2) DATA CE RESET/OE SER_EN CE/WE/OE Data Address READY PAGE_EN PAGESEL0 PAGESEL1 Reset |
Similar Part No. - AT17F32_14 |
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Similar Description - AT17F32_14 |
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