8

AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Device Addressing

The 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word

following a start condition to enable the chip for a read or write operation (see to Figure

7 on page 9).

The device address word consists of a mandatory “1”, “0” sequence for the first four

most significant bits as shown. This is common to all the Serial EEPROM devices.

The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.

These 3 bits must compare to their corresponding hardwired input pins.

The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a

memory page address bit. The two device address bits must compare to their corre-

sponding hardwired input pins. The A0 pin is no connect.

The 8K EEPROM only uses the A2 device address bit with the next two bits being for

memory page addressing. The A2 bit must compare to its corresponding hardwired

input pin. The A1 and A0 pins are no connect.

The 16K does not use any device address bits but instead the three bits are used for

memory page addressing. These page addressing bits on the 4K, 8K and 16K devices

should be considered the most significant bits of the data word address which follows.

The A0, A1 and A2 pins are no connect.

The eighth bit of the device address is the read/write operation select bit. A read opera-

tion is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a “0”. If a compare is

not made, the chip will return to a standby state.

Write Operations

BYTE WRITE: A write operation requires an 8-bit data word address following the

device address word and acknowledgment. Upon receipt of this address, the EEPROM

will again respond with a “0” and then clock in the first 8-bit data word. Following receipt

of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as

a microcontroller, must terminate the write sequence with a stop condition. At this time

the EEPROM enters an internally timed write cycle, t

inputs are disabled during this write cycle and the EEPROM will not respond until the

write is complete (see Figure 8 on page 10).

PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K

and 16K devices are capable of 16-byte page writes.

A page write is initiated the same as a byte write, but the microcontroller does not send

a stop condition after the first data word is clocked in. Instead, after the EEPROM

acknowledges receipt of the first data word, the microcontroller can transmit up to seven

(1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a “0”

after each data word received. The microcontroller must terminate the page write

sequence with a stop condition (see Figure 9 on page 10).

The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally

incremented following the receipt of each data word. The higher data word address bits

are not incremented, retaining the memory page row location. When the word address,

internally generated, reaches the page boundary, the following byte is placed at the

beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data

words are transmitted to the EEPROM, the data word address will “roll over” and previ-

ous data will be overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the

EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-