5

AT24C128SC/AT24C256SC

1661B–SEEPR–04/04

Device Operation

CLOCK AND DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-

nal device. Data on the SDA pin may change only during SCL low time periods (refer to

Data Validity timing diagram). Data changes during SCL high periods will indicate a start

or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition

which must precede any other command (refer to Start and Stop Definition timing

diagram).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.

After a read sequence, the stop command will place the EEPROM in a standby power

mode (refer to Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the

EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to

acknowledge that it has received each word.

STANDBY MODE: The AT24C128SC/256SC features a low power standby mode

which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the

completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-

wire part can be reset by following these steps:

1.

Clock up to 9 cycles.

2.

Look for SDA high in each cycle while SCL is high.

3.

Create a start condition as SDA is high.